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  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-20 20:01:04 UTC
  • Revision ID: csa@suren.me-20150420200104-b5xny65io8lvoz3w
Big redign of model structures

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ipecamera/model.h
1
 
#ifndef _IPECAMERA_MODEL_H
2
 
#define _IPECAMERA_MODEL_H
3
 
 
4
 
#include <stdio.h>
5
 
 
6
 
#include "../pcilib.h"
7
 
#include "public.h"
8
 
 
9
 
//#define IPECAMERA_DEBUG
10
 
 
11
 
#define IPECAMERA_DMA_R3
12
 
#define IPECAMERA_DMA_ADDRESS 1
13
 
#define IPECAMERA_DMA_PACKET_LENGTH 4096
14
 
 
15
 
//#define IPECAMERA_REGISTER_SPACE 0xfeaffc00
16
 
#define IPECAMERA_REGISTER_SPACE 0x9000
17
 
#define IPECAMERA_REGISTER_WRITE (IPECAMERA_REGISTER_SPACE + 0)
18
 
#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_WRITE + 16)
19
 
 
20
 
#ifdef _IPECAMERA_MODEL_C
21
 
pcilib_register_bank_description_t ipecamera_register_banks[] = {
22
 
    { PCILIB_REGISTER_BANK0,    PCILIB_BAR0,    128, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ , IPECAMERA_REGISTER_WRITE, PCILIB_LITTLE_ENDIAN, 8 , PCILIB_LITTLE_ENDIAN, "%lu"  , "cmosis", "CMOSIS CMV2000 Registers" },
23
 
    { PCILIB_REGISTER_BANK1,    PCILIB_BAR0, 0x0200, PCILIB_DEFAULT_PROTOCOL    , IPECAMERA_REGISTER_SPACE, IPECAMERA_REGISTER_SPACE, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "0x%lx", "fpga", "IPECamera Registers" },
24
 
    { PCILIB_REGISTER_BANK_DMA, PCILIB_BAR0, 0xA000, PCILIB_DEFAULT_PROTOCOL    , 0,                        0,                        PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "0x%lx", "dma", "DMA Registers"},
25
 
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
26
 
};
27
 
 
28
 
pcilib_register_description_t ipecamera_registers[] = {
29
 
{1,     0,      16,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines",  ""},
30
 
{3,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""},
31
 
{5,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""},
32
 
{7,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""},
33
 
{9,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""},
34
 
{11,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""},
35
 
{13,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""},
36
 
{15,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""},
37
 
{17,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""},
38
 
{19,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""},
39
 
{21,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""},
40
 
{23,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""},
41
 
{25,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""},
42
 
{27,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""},
43
 
{29,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""},
44
 
{31,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""},
45
 
{33,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""},
46
 
{35,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""},
47
 
{37,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""},
48
 
{39,    0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""},
49
 
{40,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""},
50
 
{41,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""},
51
 
{42,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""},
52
 
{45,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""},
53
 
{48,    0,      24,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""},
54
 
{51,    0,      24,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""},
55
 
{54,    0,      2,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""},
56
 
{55,    0,      8,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""},
57
 
{56,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""},
58
 
{59,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""},
59
 
{68,    0,      2,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""},
60
 
{69,    0,      8,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""},
61
 
{70,    0,      16,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""},
62
 
{72,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""},
63
 
{78,    0,      12,     85,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""},
64
 
{80,    0,      18,     0x3FFFF,0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""},
65
 
{82,    0,      3,      7,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""},
66
 
{89,    0,      8,      96,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""},
67
 
{90,    0,      8,      96,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""},
68
 
{100,   0,      14,     16260,  0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""},
69
 
{102,   0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""},
70
 
{103,   0,      8,      32,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""},
71
 
{111,   0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""},
72
 
{112,   0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""},
73
 
{115,   0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""},
74
 
/*{126,         0,      16,     0,                              PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "temp", ""},*/
75
 
{0x00,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
76
 
{0x10,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
77
 
{0x20,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
78
 
{0x30,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""},
79
 
{0x30,  0,      8,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_version",  ""},
80
 
{0x30,  8,      1,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_bitmode",  ""},
81
 
{0x30,  12,     2,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_resolution",  ""},
82
 
{0x30,  16,     2,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "output_mode",  ""},
83
 
{0x40,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""},
84
 
{0x50,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""},
85
 
{0x54,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""},
86
 
{0x58,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
87
 
{0x5c,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""},
88
 
{0x70,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
89
 
{0x74,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
90
 
{0x78,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""},
91
 
{0xa0,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""},
92
 
{0xa0,  0,      10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_skip_lines",  ""},
93
 
{0xa0,  10,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_num_lines",  ""},
94
 
{0xa0,  21,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_start_address",  ""},
95
 
{0xb0,  0,      32,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""},
96
 
{0xb0,  0,      11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_threshold_start_line",  ""},
97
 
{0xb0,  16,     10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_area_lines",  ""},
98
 
{0xc0,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
99
 
{0xd0,  0,      32,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_thresholds", ""},
100
 
{0xd0,  0,      10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_pixel_thr", ""},
101
 
{0xd0,  10,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_pixel_thr", ""},
102
 
{0xd0,  21,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_lines_thr", ""},
103
 
{0x100, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
104
 
{0x110, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
105
 
{0x110, 0,      16,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
106
 
{0x110, 16,     3,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature_alarms",  ""},
107
 
{0x110, 19,     10,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature",  ""},
108
 
{0x110, 29,     3,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature_alarms",  ""},
109
 
{0x120, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""},
110
 
{0x130, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""},
111
 
{0x140, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""},
112
 
{0x150, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
113
 
{0x150, 0,      5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_phi",  ""},
114
 
{0x150, 5,      5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_z",  ""},
115
 
{0x150, 10,     5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_y",  ""},
116
 
{0x150, 15,     5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_x",  ""},
117
 
{0x150, 20,     8,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_gain",  ""},
118
 
{0x160, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
119
 
{0x170, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
120
 
{0x180, 0,      32,     0x280,  0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
121
 
{0x190, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""},
122
 
{0x1a0, 0,      32,     0x64,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_max_frames", ""},
123
 
{0x1b0, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_num_frames", ""},
124
 
{0,     0,      0,      0,      0,                        0,                  0,                        0,                     NULL, NULL}
125
 
};
126
 
 
127
 
pcilib_register_range_t ipecamera_register_ranges[] = {
128
 
    {0,         128,    PCILIB_REGISTER_BANK0, 0},
129
 
    {0x9000,    0x9FFF, PCILIB_REGISTER_BANK1, -0x9000},
130
 
    {0, 0, 0, 0}
131
 
};
132
 
 
133
 
pcilib_event_description_t ipecamera_events[] = {
134
 
    {PCILIB_EVENT0, "new_frame", ""},
135
 
    {0, NULL, NULL}
136
 
};
137
 
 
138
 
pcilib_event_data_type_description_t ipecamera_data_types[] = {
139
 
    {IPECAMERA_IMAGE_DATA, PCILIB_EVENT0, "image", "16 bit pixel data" },
140
 
    {IPECAMERA_RAW_DATA, PCILIB_EVENT0, "raw", "raw data from camera" },
141
 
    {IPECAMERA_CHANGE_MASK, PCILIB_EVENT0, "cmask", "change mask" },
142
 
    {0, 0, NULL, NULL}
143
 
};
144
 
 
145
 
#else
146
 
extern pcilib_register_description_t ipecamera_registers[];
147
 
extern pcilib_register_bank_description_t ipecamera_register_banks[];
148
 
extern pcilib_register_range_t ipecamera_register_ranges[];
149
 
extern pcilib_event_description_t ipecamera_events[];
150
 
extern pcilib_event_data_type_description_t ipecamera_data_types[];
151
 
#endif 
152
 
 
153
 
#ifdef _IPECAMERA_IMAGE_C
154
 
pcilib_event_api_description_t ipecamera_image_api = {
155
 
    "ipecamera",
156
 
    
157
 
    ipecamera_init,
158
 
    ipecamera_free,
159
 
 
160
 
    ipecamera_init_dma,
161
 
 
162
 
    ipecamera_reset,
163
 
    ipecamera_start,
164
 
    ipecamera_stop,
165
 
    ipecamera_trigger,
166
 
    
167
 
    ipecamera_stream,
168
 
    ipecamera_next_event,
169
 
    ipecamera_get,
170
 
    ipecamera_return
171
 
};
172
 
#else
173
 
extern pcilib_event_api_description_t ipecamera_image_api;
174
 
#endif
175
 
 
176
 
int ipecamera_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, pcilib_register_value_t *value);
177
 
int ipecamera_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, pcilib_register_value_t value);
178
 
 
179
 
#endif /* _IPECAMERA_MODEL_H */