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  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-20 20:01:04 UTC
  • Revision ID: csa@suren.me-20150420200104-b5xny65io8lvoz3w
Big redign of model structures

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Lines of Context:
dma/ipe.h
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//#define PCILIB_NWL_MODIFICATION_IPECAMERA 0x100
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pcilib_dma_context_t *dma_ipe_init(pcilib_t *ctx, pcilib_dma_modification_t type, void *arg);
 
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pcilib_dma_context_t *dma_ipe_init(pcilib_t *ctx, const char *model, const void *arg);
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void  dma_ipe_free(pcilib_dma_context_t *vctx);
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int dma_ipe_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers);
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int dma_ipe_start(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags);
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int dma_ipe_stop(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags);
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int dma_ipe_stream_read(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, pcilib_dma_callback_t cb, void *cbattr);
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double dma_ipe_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction);
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#ifdef _PCILIB_DMA_IPE_C
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pcilib_dma_api_description_t ipe_dma_api = {
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    "ipe_dma",
 
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#ifdef _PCILIB_CONFIG_C
 
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static const pcilib_dma_api_description_t ipe_dma_api = {
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    dma_ipe_init,
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    dma_ipe_free,
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    dma_ipe_get_status,
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    dma_ipe_stream_read,
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    dma_ipe_benchmark
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};
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#else
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extern pcilib_dma_api_description_t ipe_dma_api;
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#endif
 
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static const pcilib_dma_engine_description_t ipe_dma_engines[] = {
 
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    { 0, PCILIB_DMA_TYPE_PACKET, PCILIB_DMA_FROM_DEVICE, 32, "dma", NULL },
 
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    { 0 }
 
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};
 
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static const pcilib_register_bank_description_t ipe_dma_banks[] = {
 
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    { PCILIB_REGISTER_BANK_DMA, PCILIB_BAR0, 0xA000, PCILIB_REGISTER_PROTOCOL_DEFAULT, 0,                        0,                        PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "0x%lx", "dma", "DMA Registers"},
 
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
 
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};
 
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static const pcilib_register_description_t ipe_dma_registers[] = {
 
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    {0x0000,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dcr",                        "Device Control Status Register"},
 
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    {0x0000,    0,      1,      0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "reset_dma",                      ""},
 
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    {0x0000,    16,     4,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "datapath_width",                 ""},
 
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    {0x0000,    24,     8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "fpga_family",                    ""},
 
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    {0x0004,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "ddmacr",                     "Device DMA Control Status Register"},
 
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    {0x0004,    0,      1,      0,      0xFFFFFFFF,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_start",                      "Start writting memory"},
 
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    {0x0004,    5,      1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_relxed_order",               ""},
 
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    {0x0004,    6,      1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_nosnoop",                    ""},
 
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    {0x0004,    7,      1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_int_dis",                    ""},
 
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    {0x0004,    16,     1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_start",                      ""},
 
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    {0x0004,    21,     1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_relaxed_order",              ""},
 
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    {0x0004,    22,     1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_nosnoop",                    ""},
 
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    {0x0004,    23,     1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_int_dis",                    ""},
 
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    {0x000C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_size",                   "DMA TLP size"},
 
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    {0x000C,    0,      16,     0x20,   0xFFFFFFFF,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_len",                        "Max TLP size"},
 
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    {0x000C,    16,     3,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_tlp_tc",                     "TC for TLP packets"},
 
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    {0x000C,    19,     1,      0,      0xFFFFFFFF,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_64b_en",                     "Enable 64 bit memory addressing"},
 
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    {0x000C,    20,     1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_phant_func_dis",             "Disable MWR phantom function"},
 
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    {0x000C,    24,     8,      0,      0xFFFFFFFF,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr",                    "Upper address for 64 bit memory addressing"},
 
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    {0x0010,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count",                  "Write DMA TLP Count"},
 
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    {0x0014,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern",                "DMA generator data pattern"},
 
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    {0x0028,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf",                   "MWR Performance"},
 
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    {0x003C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width",              "Negotiated and max width of PCIe Link"},
 
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    {0x003C,    0,      6,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width",          "Max link width"},
 
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    {0x003C,    8,      6,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_prg_max_lnk_width",          "Negotiated link width"},
 
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    {0x0040,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_payload_size",           ""},
 
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    {0x0040,    0,      4,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_payload_size",       "Max payload size"},
 
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    {0x0040,    8,      3,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_prg_max_payload_size",       "Prog max payload size"},
 
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    {0x0040,    16,     3,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_max_rd_req_size",            "Max read request size"},
 
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    {0x0050,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "desc_mem_din",               "Descriptor memory"},
 
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    {0x0054,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "update_addr",                "Address of progress register"},
 
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    {0x0058,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "last_descriptor_read",       "Last descriptor read by the host"},
 
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    {0x005C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "desc_mem_addr",              "Number of descriptors configured"},
 
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    {0x0060,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "update_thresh",              "Update threshold of progress register"},
 
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    {0,         0,      0,      0,      0x00000000,     0,                                           0,                        0, NULL,                         NULL}
 
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};
 
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#endif /* _PCILIB_CONFIG_C */
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#endif /* _PCILIB_DMA_IPE_H */