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Viewing changes to dma/nwl_irq.c

  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-20 20:01:04 UTC
  • Revision ID: csa@suren.me-20150420200104-b5xny65io8lvoz3w
Big redign of model structures

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Lines of Context:
dma/nwl_irq.c
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    val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    pcilib_clear_irq(ctx->pcilib, NWL_DMA_IRQ_SOURCE);
 
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    pcilib_clear_irq(ctx->dmactx.pcilib, NWL_DMA_IRQ_SOURCE);
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    if (type & PCILIB_DMA_IRQ) val |= DMA_INT_ENABLE;
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    if (type & PCILIB_EVENT_IRQ) val |= DMA_USER_INT_ENABLE;
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    uint32_t val;
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    pcilib_nwl_engine_description_t *info = ctx->engines + irq_source;
 
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    pcilib_nwl_engine_context_t *ectx = ctx->engines + irq_source;
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    if (irq_type != PCILIB_DMA_IRQ) return PCILIB_ERROR_NOTSUPPORTED;
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    if (irq_source >= ctx->n_engines) return PCILIB_ERROR_NOTAVAILABLE;
 
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    if (irq_source >= ctx->dmactx.pcilib->num_engines) return PCILIB_ERROR_NOTAVAILABLE;
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    nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
 
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    nwl_read_register(val, ctx, ectx->base_addr, REG_DMA_ENG_CTRL_STATUS);
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    if (val & DMA_ENG_INT_ACTIVE_MASK) {
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        val |= DMA_ENG_ALLINT_MASK;
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        nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
 
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        nwl_write_register(val, ctx, ectx->base_addr, REG_DMA_ENG_CTRL_STATUS);
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    }
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    return 0;