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  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-20 20:01:04 UTC
  • Revision ID: csa@suren.me-20150420200104-b5xny65io8lvoz3w
Big redign of model structures

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Lines of Context:
dma/nwl_private.h
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#define _PCILIB_DMA_NWL_PRIVATE_H
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typedef struct nwl_dma_s nwl_dma_t;
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typedef struct pcilib_nwl_engine_description_s pcilib_nwl_engine_description_t;
 
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typedef struct pcilib_nwl_engine_context_s pcilib_nwl_engine_context_t;
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#define NWL_DMA_IRQ_SOURCE 0
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#include "nwl.h"
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#include "nwl_irq.h"
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#include "nwl_register.h"
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#include "nwl_engine.h"
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#include "nwl_loopback.h"
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#define nwl_read_register(var, ctx, base, reg) pcilib_datacpy(&var, base + reg, 4, 1, ctx->dma_bank->raw_endianess)
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#define nwl_write_register(var, ctx, base, reg) pcilib_datacpy(base + reg, &var, 4, 1, ctx->dma_bank->raw_endianess)
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struct pcilib_nwl_engine_description_s {
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    pcilib_dma_engine_description_t desc;
 
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struct pcilib_nwl_engine_context_s {
 
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    const pcilib_dma_engine_description_t *desc;
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    char *base_addr;
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    size_t ring_size, page_size;
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    size_t head, tail;
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    pcilib_kmem_handle_t *ring;
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    int preserve;                       /**< indicates that DMA should not be stopped during clean-up */
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};
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typedef enum {
 
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    NWL_MODIFICATION_DEFAULT,
 
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    NWL_MODIFICATION_IPECAMERA
 
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} nwl_modification_t;
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struct nwl_dma_s {
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    struct pcilib_dma_context_s dmactx;
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    pcilib_t *pcilib;
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    pcilib_dma_modification_t type;
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    pcilib_register_bank_description_t *dma_bank;
 
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    pcilib_dma_context_t dmactx;
 
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    nwl_modification_t type;
 
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    int ignore_eop;                     /**< always set end-of-packet */
 
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    const pcilib_register_bank_description_t *dma_bank;
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    char *base_addr;
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    pcilib_irq_type_t irq_enabled;      /**< indicates that IRQs are enabled */
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    int irq_started;                    /**< indicates that IRQ subsystem is initialized (detecting which types should be preserverd) */    
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    int loopback_started;               /**< indicates that benchmarking subsystem is initialized */
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    pcilib_dma_engine_t n_engines;
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    pcilib_nwl_engine_description_t engines[PCILIB_MAX_DMA_ENGINES + 1];
 
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//    pcilib_dma_engine_t n_engines;
 
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    pcilib_nwl_engine_context_t engines[PCILIB_MAX_DMA_ENGINES + 1];
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};
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int nwl_add_registers(nwl_dma_t *ctx);
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#endif /* _PCILIB_DMA_NWL_PRIVATE_H */