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  • Committer: Suren A. Chilingaryan
  • Date: 2011-07-09 03:33:18 UTC
  • Revision ID: csa@dside.dyndns.org-20110709033318-2k7vk5s5p5u7btem
Support dynamic registers, support register offsets and multiregisters (bitmasks), list NWL DMA registers

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Lines of Context:
dma/nwl_register.h
 
1
/*
 
2
pcilib_register_bank_description_t ipecamera_register_banks[] = {
 
3
    { PCILIB_REGISTER_DMABANK0, PCILIB_BAR0, 128, PCILIB_DEFAULT_PROTOCOL, DMA_NWL_OFFSET, DMA_NWL_OFFSET, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "%lx", "dma", "NorthWest Logick DMA Engine" },
 
4
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
 
5
};
 
6
*/
 
7
 
 
8
  // DMA
 
9
static pcilib_register_description_t nwl_dma_registers[] = {
 
10
    {0x4000,    0,      32,     0,      0x00000011,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_control_and_status",  ""},
 
11
    {0x4000,    0,      1,      0,      0x00000011,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_enable",  ""},
 
12
    {0x4000,    1,      1,      0,      0x00000011,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_active",  ""},
 
13
    {0x4000,    2,      1,      0,      0x00000011,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_pending",  ""},
 
14
    {0x4000,    3,      1,      0,      0x00000011,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_mode",  ""},
 
15
    {0x4000,    4,      1,      0,      0x00000011,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_user_interrupt_enable",  ""},
 
16
    {0x4000,    5,      1,      0,      0x00000011,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_user_interrupt_active",  ""},
 
17
    {0x4000,    16,     8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_s2c_interrupt_status",  ""},
 
18
    {0x4000,    24,     8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_c2s_interrupt_status",  ""},
 
19
    {0x8000,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_design_version",  ""},
 
20
    {0x8000,    0,      4,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_subversion_number",  ""},
 
21
    {0x8000,    4,      8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_version_number",  ""},
 
22
    {0x8000,    28,     4,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_targeted_device",  ""},
 
23
    {0x8200,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_transmit_utilization",  ""},
 
24
    {0x8200,    0,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_transmit_sample_count",  ""},
 
25
    {0x8200,    2,      30,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_transmit_dword_count",  ""},
 
26
    {0x8204,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_receive_utilization",  ""},
 
27
    {0x8004,    0,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_receive_sample_count",  ""},
 
28
    {0x8004,    2,      30,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_receive_dword_count",  ""},
 
29
    {0x8208,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_mwr",  ""},
 
30
    {0x8008,    0,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_mwr_sample_count",  ""},
 
31
    {0x8008,    2,      30,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_mwr_dword_count",  ""},
 
32
    {0x820C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_cpld",  ""},
 
33
    {0x820C,    0,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_cpld_sample_count",  ""},
 
34
    {0x820C,    2,      30,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_cpld_dword_count",  ""},
 
35
    {0x8210,    0,      12,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_cpld",  ""},
 
36
    {0x8214,    0,      8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_cplh",  ""},
 
37
    {0x8218,    0,      12,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_npd",  ""},
 
38
    {0x821C,    0,      8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_nph",  ""},
 
39
    {0x8220,    0,      12,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_pd",  ""},
 
40
    {0x8224,    0,      8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_ph",  ""},
 
41
    {0,         0,      0,      0,      0x00000000,     0,                                           0,                        0, NULL, NULL}
 
42
};
 
43
 
 
44
 // DMA Engine Registers
 
45
#define NWL_MAX_DMA_ENGINE_REGISTERS 64
 
46
#define NWL_MAX_REGISTER_NAME 128
 
47
static char nwl_dma_engine_register_names[PCILIB_MAX_DMA_ENGINES * NWL_MAX_DMA_ENGINE_REGISTERS][NWL_MAX_REGISTER_NAME];
 
48
static pcilib_register_description_t nwl_dma_engine_registers[] = {
 
49
    {0x0000,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_engine_capabilities",  ""},
 
50
    {0x0000,    0,      1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_present",  ""},
 
51
    {0x0000,    1,      1,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_direction",  ""},
 
52
    {0x0000,    4,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_type",  ""},
 
53
    {0x0000,    8,      8,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_number",  ""},
 
54
    {0x0000,    24,     6,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_max_buffer_size",  ""},
 
55
    {0x0004,    0,      32,     0,      0x0000C100,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_engine_control",  ""},
 
56
    {0x0004,    0,      1,      0,      0x0000C100,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_interrupt_enable",  ""},
 
57
    {0x0004,    1,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_interrupt_active",  ""},
 
58
    {0x0004,    2,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_complete",  ""},
 
59
    {0x0004,    3,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_alignment_error",  ""},
 
60
    {0x0004,    4,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_fetch_error",  ""},
 
61
    {0x0004,    5,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sw_abort_error",  ""},
 
62
    {0x0004,    8,      1,      0,      0x0000C100,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_enable",  ""},
 
63
    {0x0004,    9,      1,      0,      0x0000C100,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_running",  ""},
 
64
    {0x0004,    10,     1,      0,      0x0000C100,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_waiting",  ""},
 
65
    {0x0004,    14,     1,      0,      0x0000C100,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset_request", ""},
 
66
    {0x0004,    15,     1,      0,      0x0000C100,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset", ""},
 
67
    {0x0008,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_next_descriptor",  ""},
 
68
    {0x000C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_RW  , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sw_descriptor",  ""},
 
69
    {0x0010,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_last_descriptor",  ""},
 
70
    {0x0014,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_active_time",  ""},
 
71
    {0x0018,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_wait_time",  ""},
 
72
    {0x001C,    0,      32,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_counter",  ""},
 
73
    {0x001C,    0,      2,      0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sample_count",  ""},
 
74
    {0x001C,    2,      30,     0,      0x00000000,     PCILIB_REGISTER_R   , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_dword_count",  ""},
 
75
    {0,         0,      0,      0,      0x00000000,     0,                                          0,                        0, NULL, NULL}
 
76
};
 
77
 
 
78
/*
 
79
 // XAUI registers
 
80
static pcilib_register_description_t nwl_xaui_registers[] = {
 
81
    {0,         0,      0,      0,      0,                                          0,                        0, NULL, NULL}
 
82
};
 
83
*/
 
84
 
 
85
 // XRAWDATA registers
 
86
static pcilib_register_description_t nwl_xrawdata_registers[] = {
 
87
    {0x9100,    0,      1,      0,      0x00000000,     PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_generator",  ""},
 
88
    {0x9104,    0,      16,     0,      0x00000000,     PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_packet_length",  ""},
 
89
    {0x9108,    0,      2,      0,      0x00000003,     PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_control",  ""},
 
90
    {0x9108,    0,      1,      0,      0x00000003,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_checker",  ""},
 
91
    {0x9108,    1,      1,      0,      0x00000003,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_loopback",  ""},
 
92
    {0x910C,    0,      1,      0,      0x00000000,     PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_data_mistmatch",  ""},
 
93
    {0,         0,      0,      0,      0x00000000,     0,                                            0,                        0, NULL, NULL}
 
94
};