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int dma_nwl_acknowledge_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t irq_type, pcilib_irq_source_t irq_source) {
106
nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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pcilib_nwl_engine_description_t *info = ctx->engines + irq_source;
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if (irq_type != PCILIB_DMA_IRQ) return PCILIB_ERROR_NOTSUPPORTED;
110
if (irq_source >= ctx->n_engines) return PCILIB_ERROR_NOTAVAILABLE;
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nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
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if (val & DMA_ENG_INT_ACTIVE_MASK) {
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val |= DMA_ENG_ALLINT_MASK;
115
nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);