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Viewing changes to dma/nwl_engine.c

  • Committer: Suren A. Chilingaryan
  • Date: 2011-07-18 14:42:51 UTC
  • Revision ID: csa@dside.dyndns.org-20110718144251-nmbl7xhcq00mfx1p
IRQ acknowledgement support in the engine API

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Lines of Context:
dma/nwl_engine.c
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    if (info->reused) {
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        info->preserve = 1;
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            // Acknowledge asserted engine interrupts    
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        nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
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        if (val & DMA_ENG_INT_ACTIVE_MASK) {
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            val |= DMA_ENG_ALLINT_MASK;
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            nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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        }
 
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        dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma);
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#ifdef NWL_GENERATE_DMA_IRQ
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        dma_nwl_enable_engine_irq(ctx, dma);
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            return PCILIB_ERROR_TIMEOUT;
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        }
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            // Acknowledge asserted engine interrupts    
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        if (val & DMA_ENG_INT_ACTIVE_MASK) {
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            val |= DMA_ENG_ALLINT_MASK;
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            nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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        }
 
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        dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma);
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        ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring);
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        nwl_write_register(ring_pa, ctx, info->base_addr, REG_DMA_ENG_NEXT_BD);
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            nwl_write_register(ring_pa, ctx, info->base_addr, REG_SW_NEXT_BD);
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        }
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    }
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        // Acknowledge asserted engine interrupts    
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    if (val & DMA_ENG_INT_ACTIVE_MASK) {
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        val |= DMA_ENG_ALLINT_MASK;
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        nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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    }
 
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    dma_nwl_acknowledge_irq(ctx, PCILIB_DMA_IRQ, dma);
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    if (info->preserve) {
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        flags = PCILIB_KMEM_FLAG_REUSE;