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Viewing changes to dma/nwl_irq.c

  • Committer: Suren A. Chilingaryan
  • Date: 2011-07-12 12:39:06 UTC
  • Revision ID: csa@dside.dyndns.org-20110712123906-4tas2h34i0b2tkp8
Provide IRQ enable/disable call

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Lines of Context:
dma/nwl_irq.c
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#include "nwl.h"
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#include "nwl_defines.h"
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int dma_nwl_enable_irq(nwl_dma_t *ctx, pcilib_irq_type_t type) {
 
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int dma_nwl_init_irq(nwl_dma_t *ctx, uint32_t val) {
 
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    if (val&(DMA_INT_ENABLE|DMA_USER_INT_ENABLE)) {
 
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        if (val&DMA_INT_ENABLE) ctx->irq_preserve |= PCILIB_DMA_IRQ;
 
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        if (val&DMA_USER_INT_ENABLE) ctx->irq_preserve |= PCILIB_EVENT_IRQ;
 
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    }
 
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    ctx->irq_init = 1;
 
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    return 0;
 
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}
 
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int dma_nwl_free_irq(nwl_dma_t *ctx) {
 
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    if (ctx->irq_init) {
 
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        dma_nwl_disable_irq((pcilib_dma_context_t*)ctx, 0);
 
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        if (ctx->irq_preserve) dma_nwl_enable_irq((pcilib_dma_context_t*)ctx, ctx->irq_preserve, 0);
 
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        ctx->irq_enabled = 0;
 
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        ctx->irq_init = 0;
 
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    }
 
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    return 0;
 
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}
 
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int dma_nwl_enable_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t type, pcilib_dma_flags_t flags) {
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    uint32_t val;
 
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    if (flags&PCILIB_DMA_FLAG_PERMANENT) ctx->irq_preserve |= type;
 
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    if (ctx->irq_enabled == type) return 0;
 
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    type |= ctx->irq_enabled;
 
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    nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
 
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    if (!ctx->irq_init) dma_nwl_init_irq(ctx, val);
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    nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    return 0;
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}
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int dma_nwl_disable_irq(nwl_dma_t *ctx) {
 
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int dma_nwl_disable_irq(pcilib_dma_context_t *vctx, pcilib_dma_flags_t flags) {
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    uint32_t val;
 
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    ctx->irq_enabled = 0;
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    nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
 
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    if (!ctx->irq_init) dma_nwl_init_irq(ctx, val);
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    val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    if (flags&PCILIB_DMA_FLAG_PERMANENT) ctx->irq_preserve = 0;
 
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    return 0;
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}
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int dma_nwl_enable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma) {
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    uint32_t val;
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    dma_nwl_enable_irq(ctx, ctx->irq_enabled|PCILIB_DMA_IRQ);
 
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    dma_nwl_enable_irq(ctx, ctx->irq_enabled|PCILIB_DMA_IRQ, 0);
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    nwl_read_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS);
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    val |= (DMA_ENG_INT_ENABLE);
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}
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// ACK