/alps/pcitool : revision 43

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#define _PCILIB_DMA_NWL_C

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#include <stdio.h>

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#include <stdlib.h>

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#include <string.h>

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#include "pci.h"

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#include "pcilib.h"

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#include "error.h"

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#include "tools.h"

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#include "nwl.h"

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/* Common DMA registers */

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#define REG_DMA_CTRL_STATUS 0x4000 /**< DMA Common Ctrl & Status */

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/* These engine registers are applicable to both S2C and C2S channels.

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* Register field mask and shift definitions are later in this file.

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*/

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#define REG_DMA_ENG_CAP 0x00000000 /**< DMA Engine Capabilities */

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#define REG_DMA_ENG_CTRL_STATUS 0x00000004 /**< DMA Engine Control */

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#define REG_DMA_ENG_NEXT_BD 0x00000008 /**< HW Next desc pointer */

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#define REG_SW_NEXT_BD 0x0000000C /**< SW Next desc pointer */

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#define REG_DMA_ENG_LAST_BD 0x00000010 /**< HW Last completed pointer */

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#define REG_DMA_ENG_ACTIVE_TIME 0x00000014 /**< DMA Engine Active Time */

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#define REG_DMA_ENG_WAIT_TIME 0x00000018 /**< DMA Engine Wait Time */

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#define REG_DMA_ENG_COMP_BYTES 0x0000001C /**< DMA Engine Completed Bytes */

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/* Register masks. The following constants define bit locations of various

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* control bits in the registers. For further information on the meaning of

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* the various bit masks, refer to the hardware spec.

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*

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* Masks have been written assuming HW bits 0-31 correspond to SW bits 0-31

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*/

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/** @name Bitmasks of REG_DMA_CTRL_STATUS register.

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* @{

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*/

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#define DMA_INT_ENABLE 0x00000001 /**< Enable global interrupts */

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#define DMA_INT_DISABLE 0x00000000 /**< Disable interrupts */

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#define DMA_INT_ACTIVE_MASK 0x00000002 /**< Interrupt active? */

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#define DMA_INT_PENDING_MASK 0x00000004 /**< Engine interrupt pending */

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#define DMA_INT_MSI_MODE 0x00000008 /**< MSI or Legacy mode? */

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#define DMA_USER_INT_ENABLE 0x00000010 /**< Enable user interrupts */

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#define DMA_USER_INT_ACTIVE_MASK 0x00000020 /**< Int - user interrupt */

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#define DMA_USER_INT_ACK 0x00000020 /**< Acknowledge */

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#define DMA_MPS_USED 0x00000700 /**< MPS Used */

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#define DMA_MRRS_USED 0x00007000 /**< MRRS Used */

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#define DMA_S2C_ENG_INT_VAL 0x00FF0000 /**< IRQ value of 1st 8 S2Cs */

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#define DMA_C2S_ENG_INT_VAL 0xFF000000 /**< IRQ value of 1st 8 C2Ss */

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/** @name Bitmasks of REG_DMA_ENG_CAP register.

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* @{

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*/

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/* DMA engine characteristics */

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#define DMA_ENG_PRESENT_MASK 0x00000001 /**< DMA engine present? */

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#define DMA_ENG_DIRECTION_MASK 0x00000002 /**< DMA engine direction */

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#define DMA_ENG_C2S 0x00000002 /**< DMA engine - C2S */

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#define DMA_ENG_S2C 0x00000000 /**< DMA engine - S2C */

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#define DMA_ENG_TYPE_MASK 0x00000030 /**< DMA engine type */

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#define DMA_ENG_BLOCK 0x00000000 /**< DMA engine - Block type */

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#define DMA_ENG_PACKET 0x00000010 /**< DMA engine - Packet type */

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#define DMA_ENG_NUMBER 0x0000FF00 /**< DMA engine number */

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#define DMA_ENG_BD_MAX_BC 0x3F000000 /**< DMA engine max buffer size */

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/* Shift constants for selected masks */

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#define DMA_ENG_NUMBER_SHIFT 8

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#define DMA_ENG_BD_MAX_BC_SHIFT 24

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#define DMA_ENGINE_PER_SIZE 0x100 /**< Separation between engine regs */

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#define DMA_OFFSET 0 /**< Starting register offset */

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/**< Size of DMA engine reg space */

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#define DMA_SIZE (MAX_DMA_ENGINES * DMA_ENGINE_PER_SIZE)

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/*

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pcilib_register_bank_description_t ipecamera_register_banks[] = {

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{ PCILIB_REGISTER_DMABANK0, PCILIB_BAR0, 128, PCILIB_DEFAULT_PROTOCOL, DMA_NWL_OFFSET, DMA_NWL_OFFSET, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "%lx", "dma", "NorthWest Logick DMA Engine" },

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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }

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};

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pcilib_register_description_t dma_nwl_registers[] = {

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{0, 0, 32, 0, PCILIB_REGISTER_R , PCILIB_REGISTER_DMABANK, "dma_capabilities", ""},

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{1, 0, 32, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_DMABANK, "dma_control", ""},

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};

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*/

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typedef struct {

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pcilib_dma_engine_description_t desc;

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char *base_addr;

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} pcilib_nwl_engine_description_t;

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struct nwl_dma_s {

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pcilib_t *pcilib;

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pcilib_register_bank_description_t *dma_bank;

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char *base_addr;

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pcilib_nwl_engine_description_t engines[PCILIB_MAX_DMA_ENGINES + 1];

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};

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#define nwl_read_register(var, ctx, base, reg) pcilib_datacpy(&var, base + reg, 4, 1, ctx->dma_bank->raw_endianess)

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#define nwl_write_register(var, ctx, base, reg) pcilib_datacpy(base + reg, &var, 4, 1, ctx->dma_bank->raw_endianess)

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static int nwl_read_engine_config(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, char *base) {

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uint32_t val;

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nwl_read_register(val, ctx, base, REG_DMA_ENG_CAP);

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if ((val & DMA_ENG_PRESENT_MASK) == 0) return PCILIB_ERROR_NOTAVAILABLE;

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info->desc.addr = (val & DMA_ENG_NUMBER) >> DMA_ENG_NUMBER_SHIFT;

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switch (val & DMA_ENG_DIRECTION_MASK) {

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case DMA_ENG_C2S:

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info->desc.direction = PCILIB_DMA_FROM_DEVICE;

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break;

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default:

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info->desc.direction = PCILIB_DMA_TO_DEVICE;

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}

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switch (val & DMA_ENG_TYPE_MASK) {

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case DMA_ENG_BLOCK:

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info->desc.type = PCILIB_DMA_TYPE_BLOCK;

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break;

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case DMA_ENG_PACKET:

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info->desc.type = PCILIB_DMA_TYPE_PACKET;

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break;

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default:

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info->desc.type = PCILIB_DMA_TYPE_UNKNOWN;

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}

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info->desc.addr_bits = (val & DMA_ENG_BD_MAX_BC) >> DMA_ENG_BD_MAX_BC_SHIFT;

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return 0;

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}

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pcilib_dma_context_t *dma_nwl_init(pcilib_t *pcilib) {

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int i;

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int err;

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pcilib_dma_t n_engines;

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pcilib_model_description_t *model_info = pcilib_get_model_description(pcilib);

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nwl_dma_t *ctx = malloc(sizeof(nwl_dma_t));

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if (ctx) {

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memset(ctx, 0, sizeof(nwl_dma_t));

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ctx->pcilib = pcilib;

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pcilib_register_bank_t dma_bank = pcilib_find_bank_by_addr(pcilib, PCILIB_REGISTER_BANK_DMA);

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if (dma_bank == PCILIB_REGISTER_BANK_INVALID) {

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pcilib_error("DMA Register Bank could not be found");

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return NULL;

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}

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ctx->dma_bank = model_info->banks + dma_bank;

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ctx->base_addr = pcilib_resolve_register_address(pcilib, ctx->dma_bank->bar, ctx->dma_bank->read_addr);

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for (i = 0, n_engines = 0; i < 2 * PCILIB_MAX_DMA_ENGINES; i++) {

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char *addr = ctx->base_addr + DMA_OFFSET + i * DMA_ENGINE_PER_SIZE;

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err = nwl_read_engine_config(ctx, ctx->engines + n_engines, addr);

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if (!err) {

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ctx->engines[n_engines].base_addr = addr;

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pcilib_set_dma_engine_description(pcilib, n_engines, (pcilib_dma_engine_description_t*)(ctx->engines + n_engines));

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++n_engines;

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}

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}

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pcilib_set_dma_engine_description(pcilib, n_engines, NULL);

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}

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return (pcilib_dma_context_t*)ctx;

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}

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void dma_nwl_free(pcilib_dma_context_t *vctx) {

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nwl_dma_t *ctx = (nwl_dma_t*)vctx;

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if (ctx) {

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free(ctx);

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}

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}