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Viewing changes to xml/test/camera.xml

  • Committer: Suren A. Chilingaryan
  • Date: 2015-09-24 02:28:45 UTC
  • mfrom: (305.1.19 views)
  • Revision ID: csa@suren.me-20150924022845-p7hc8lh8v0q48g0r
Finalyze XML support and provide initial support for views (only descriptions so far)

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xml/test/camera.xml
1
 
<?xml version="1.0" encoding="ISO-8859-1"?>
 
1
<?xml version="1.0"?>
2
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<model xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
3
 
  <banks>
4
 
    <bank>
5
 
      <bank_description>
6
 
        <bar>0</bar>
7
 
        <size>0x0200</size>
8
 
        <protocol>software_registers</protocol>
9
 
        <read_address>0x9000</read_address>
10
 
        <write_address>0x9000</write_address>
11
 
        <word_size>32</word_size>
12
 
        <endianess>little</endianess>
13
 
        <format>0x%lx</format>
14
 
        <name>software</name>
15
 
        <description>IPECamera Registers</description>
16
 
      </bank_description>
17
 
      <registers>
18
 
        <register>
19
 
          <address>0x00</address>
20
 
          <offset>0</offset>
21
 
          <size>32</size>
22
 
          <default>0</default>
23
 
          <rwmask>0</rwmask>
24
 
          <mode>RW</mode>
25
 
          <name>spi_conf_input</name>
26
 
        </register>
27
 
        <register>
28
 
          <address>0x10</address>
29
 
          <offset>0</offset>
30
 
          <size>32</size>
31
 
          <default>0</default>
32
 
          <rwmask>0</rwmask>
33
 
          <mode>R</mode>
34
 
          <name>spi_conf_output</name>
35
 
        </register>
36
 
        <register>
37
 
          <address>0x20</address>
38
 
          <offset>0</offset>
39
 
          <size>32</size>
40
 
          <default>0</default>
41
 
          <rwmask>0</rwmask>
42
 
          <mode>RW</mode>
43
 
          <name>spi_clk_speed</name>
44
 
        </register>
45
 
        <register>
46
 
          <address>0x30</address>
47
 
          <offset>0</offset>
48
 
          <size>32</size>
49
 
          <default>0</default>
50
 
          <rwmask>0</rwmask>
51
 
          <mode>R</mode>
52
 
          <name>firmware_info</name>
53
 
          <registers_bits>
54
 
            <register_bits>
55
 
              <offset>0</offset>
56
 
              <size>8</size>
57
 
              <mode>R</mode>
58
 
              <name>firmware_version</name>
59
 
            </register_bits>
60
 
            <register_bits>
61
 
              <offset>8</offset>
62
 
              <size>1</size>
63
 
              <mode>R</mode>
64
 
              <name>firmware_bitmode</name>
65
 
            </register_bits>
66
 
            <register_bits>
67
 
              <offset>12</offset>
68
 
              <size>2</size>
69
 
              <mode>R</mode>
70
 
              <name>adc_resolution</name>
71
 
            </register_bits>
72
 
            <register_bits>
73
 
              <offset>16</offset>
74
 
              <size>2</size>
75
 
              <mode>R</mode>
76
 
              <name>output_mode</name>
77
 
            </register_bits>
78
 
          </registers_bits>
79
 
        </register>
80
 
        <register>
81
 
          <address>0x40</address>
82
 
          <offset>0</offset>
83
 
          <size>32</size>
84
 
          <default>0</default>
85
 
          <rwmask>0</rwmask>
86
 
          <mode>RW</mode>
87
 
          <name>control</name>
88
 
                <registers_bits>
89
 
                    <register_bits>
90
 
                        <offset>31</offset>
91
 
                        <size>1</size>
92
 
                        <mode>R</mode>
93
 
                        <name>freq</name>
94
 
                    </register_bits>
95
 
                </registers_bits>       
96
 
        </register>
97
 
        <register>
98
 
          <address>0x50</address>
99
 
          <offset>0</offset>
100
 
          <size>32</size>
101
 
          <default>0</default>
102
 
          <rwmask>0</rwmask>
103
 
          <mode>R</mode>
104
 
          <name>status</name>
105
 
        </register>
106
 
        <register>
107
 
          <address>0x54</address>
108
 
          <offset>0</offset>
109
 
          <size>32</size>
110
 
          <default>0</default>
111
 
          <rwmask>0</rwmask>
112
 
          <mode>R</mode>
113
 
          <name>status2</name>
114
 
        </register>
115
 
        <register>
116
 
          <address>0x58</address>
117
 
          <offset>0</offset>
118
 
          <size>32</size>
119
 
          <default>0</default>
120
 
          <rwmask>0</rwmask>
121
 
          <mode>R</mode>
122
 
          <name>status3</name>
123
 
        </register>
124
 
        <register>
125
 
          <address>0x5c</address>
126
 
          <offset>0</offset>
127
 
          <size>32</size>
128
 
          <default>0</default>
129
 
          <rwmask>0</rwmask>
130
 
          <mode>R</mode>
131
 
          <name>fr_status</name>
132
 
        </register>
133
 
        <register>
134
 
          <address>0x70</address>
135
 
          <offset>0</offset>
136
 
          <size>32</size>
137
 
          <default>0</default>
138
 
          <rwmask>0</rwmask>
139
 
          <mode>R</mode>
140
 
          <name>start_address</name>
141
 
        </register>
142
 
        <register>
143
 
          <address>0x74</address>
144
 
          <offset>0</offset>
145
 
          <size>32</size>
146
 
          <default>0</default>
147
 
          <rwmask>0</rwmask>
148
 
          <mode>R</mode>
149
 
          <name>end_address</name>
150
 
        </register>
151
 
        <register>
152
 
          <address>0x78</address>
153
 
          <offset>0</offset>
154
 
          <size>32</size>
155
 
          <default>0</default>
156
 
          <rwmask>0</rwmask>
157
 
          <mode>R</mode>
158
 
          <name>rd_address</name>
159
 
        </register>
160
 
        <register>
161
 
          <address>0xa0</address>
162
 
          <offset>0</offset>
163
 
          <size>32</size>
164
 
          <default>0</default>
165
 
          <rwmask>0</rwmask>
166
 
          <mode>R</mode>
167
 
          <name>fr_param1</name>
168
 
          <registers_bits>
169
 
            <register_bits>
170
 
              <offset>0</offset>
171
 
              <size>10</size>
172
 
              <mode>RW</mode>
173
 
              <name>fr_skip_lines</name>
174
 
            </register_bits>
175
 
            <register_bits>
176
 
              <offset>10</offset>
177
 
              <size>11</size>
178
 
              <mode>RW</mode>
179
 
              <name>fr_num_lines</name>
180
 
            </register_bits>
181
 
            <register_bits>
182
 
              <offset>21</offset>
183
 
              <size>11</size>
184
 
              <mode>RW</mode>
185
 
              <name>fr_start_address</name>
186
 
            </register_bits>
187
 
          </registers_bits>
188
 
        </register>
189
 
        <register>
190
 
          <address>0xb0</address>
191
 
          <offset>0</offset>
192
 
          <size>32</size>
193
 
          <default>0</default>
194
 
          <rwmask>all</rwmask>
195
 
          <mode>RW</mode>
196
 
          <name>fr_param2</name>
197
 
          <registers_bits>
198
 
            <register_bits>
199
 
              <offset>0</offset>
200
 
              <size>11</size>
201
 
              <mode>RW</mode>
202
 
              <name>fr_threshold_start_line</name>
203
 
            </register_bits>
204
 
            <register_bits>
205
 
              <offset>16</offset>
206
 
              <size>10</size>
207
 
              <mode>RW</mode>
208
 
              <name>fr_area_lines</name>
209
 
            </register_bits>
210
 
          </registers_bits>
211
 
        </register>
212
 
        <register>
213
 
          <address>0xc0</address>
214
 
          <offset>0</offset>
215
 
          <size>32</size>
216
 
          <default>0</default>
217
 
          <rwmask>0</rwmask>
218
 
          <mode>R</mode>
219
 
          <name>skiped_lines</name>
220
 
        </register>
221
 
        <register>
222
 
          <address>0xd0</address>
223
 
          <offset>0</offset>
224
 
          <size>32</size>
225
 
          <default>0</default>
226
 
          <rwmask>all</rwmask>
227
 
          <mode>RW</mode>
228
 
          <name>fr_thresholds</name>
229
 
        </register>
230
 
        <register>
231
 
          <address>0xd0</address>
232
 
          <offset>0</offset>
233
 
          <size>10</size>
234
 
          <default>0</default>
235
 
          <rwmask>all</rwmask>
236
 
          <mode>RW</mode>
237
 
          <name>fr_pixel_thr</name>
238
 
        </register>
239
 
        <register>
240
 
          <address>0xd0</address>
241
 
          <offset>10</offset>
242
 
          <size>11</size>
243
 
          <default>0</default>
244
 
          <rwmask>all</rwmask>
245
 
          <mode>RW</mode>
246
 
          <name>fr_num_pixel_thr</name>
247
 
        </register>
248
 
        <register>
249
 
          <address>0xd0</address>
250
 
          <offset>21</offset>
251
 
          <size>11</size>
252
 
          <default>0</default>
253
 
          <rwmask>all</rwmask>
254
 
          <mode>RW</mode>
255
 
          <name>fr_num_lines_thr</name>
256
 
        </register>
257
 
        <register>
258
 
          <address>0x100</address>
259
 
          <offset>0</offset>
260
 
          <size>32</size>
261
 
          <default>0</default>
262
 
          <rwmask>0</rwmask>
263
 
          <mode>RW</mode>
264
 
          <name>rawdata_pkt_addr</name>
265
 
        </register>
266
 
        <register>
267
 
          <address>0x110</address>
268
 
          <offset>0</offset>
269
 
          <size>32</size>
270
 
          <default>0</default>
271
 
          <rwmask>0</rwmask>
272
 
          <mode>R</mode>
273
 
          <name>temperature_info</name>
274
 
          <registers_bits>
275
 
            <register_bits>
276
 
              <offset>0</offset>
277
 
              <size>16</size>
278
 
              <mode>R</mode>
279
 
              <name>sensor_temperature</name>
280
 
                <views>
281
 
                <view>formuu1</view>
282
 
                <view>formuu2</view>
283
 
                <view>enumm2</view>
284
 
              </views>
285
 
            </register_bits>
286
 
            <register_bits>
287
 
              <offset>16</offset>
288
 
              <size>3</size>
289
 
              <mode>R</mode>
290
 
              <name>sensor_temperature_alarms</name>
291
 
            </register_bits>
292
 
            <register_bits>
293
 
              <offset>19</offset>
294
 
              <size>10</size>
295
 
              <mode>RW</mode>
296
 
              <name>fpga_temperature</name>
297
 
              <views>
298
 
                <view>formuu1</view>
299
 
                <view>enumm1</view>
300
 
              </views>
301
 
            </register_bits>
302
 
            <register_bits>
303
 
              <offset>29</offset>
304
 
              <size>3</size>
305
 
              <mode>R</mode>
306
 
              <name>fpga_temperature_alarms</name>
307
 
            </register_bits>
308
 
          </registers_bits>
309
 
        </register>
310
 
        <register>
311
 
          <address>0x120</address>
312
 
          <offset>0</offset>
313
 
          <size>32</size>
314
 
          <default>0</default>
315
 
          <rwmask>0</rwmask>
316
 
          <mode>R</mode>
317
 
          <name>num_lines</name>
318
 
        </register>
319
 
        <register>
320
 
          <address>0x130</address>
321
 
          <offset>0</offset>
322
 
          <size>32</size>
323
 
          <default>0</default>
324
 
          <rwmask>0</rwmask>
325
 
          <mode>R</mode>
326
 
          <name>start_line</name>
327
 
        </register>
328
 
        <register>
329
 
          <address>0x140</address>
330
 
          <offset>0</offset>
331
 
          <size>32</size>
332
 
          <default>0</default>
333
 
          <rwmask>0</rwmask>
334
 
          <mode>R</mode>
335
 
          <name>exp_time</name>
336
 
        </register>
337
 
        <register>
338
 
          <address>0x150</address>
339
 
          <offset>0</offset>
340
 
          <size>32</size>
341
 
          <default>0</default>
342
 
          <rwmask>0</rwmask>
343
 
          <mode>RW</mode>
344
 
          <name>motor</name>
345
 
          <registers_bits>
346
 
            <register_bits>
347
 
              <offset>0</offset>
348
 
              <size>5</size>
349
 
              <mode>RW</mode>
350
 
              <name>motor_phi</name>
351
 
            </register_bits>
352
 
            <register_bits>
353
 
              <offset>5</offset>
354
 
              <size>5</size>
355
 
              <mode>RW</mode>
356
 
              <name>motor_z</name>
357
 
            </register_bits>
358
 
            <register_bits>
359
 
              <offset>10</offset>
360
 
              <size>5</size>
361
 
              <mode>RW</mode>
362
 
              <name>motor_y</name>
363
 
            </register_bits>
364
 
            <register_bits>
365
 
              <offset>15</offset>
366
 
              <size>5</size>
367
 
              <mode>RW</mode>
368
 
              <name>motor_x</name>
369
 
            </register_bits>
370
 
            <register_bits>
371
 
              <offset>20</offset>
372
 
              <size>8</size>
373
 
              <mode>R</mode>
374
 
              <name>adc_gain</name>
375
 
            </register_bits>
376
 
          </registers_bits>
377
 
        </register>
378
 
        <register>
379
 
          <address>0x160</address>
380
 
          <offset>0</offset>
381
 
          <size>32</size>
382
 
          <default>0</default>
383
 
          <rwmask>0</rwmask>
384
 
          <mode>R</mode>
385
 
          <name>write_status</name>
386
 
        </register>
387
 
        <register>
388
 
          <address>0x170</address>
389
 
          <offset>0</offset>
390
 
          <size>32</size>
391
 
          <default>0</default>
392
 
          <rwmask>0</rwmask>
393
 
          <mode>RW</mode>
394
 
          <name>num_triggers</name>
395
 
        </register>
396
 
        <register>
397
 
          <address>0x180</address>
398
 
          <offset>0</offset>
399
 
          <size>32</size>
400
 
          <default>0x280</default>
401
 
          <rwmask>0</rwmask>
402
 
          <mode>RW</mode>
403
 
          <name>trigger_period</name>
404
 
          <views>
405
 
                <view>enumm2</view>
406
 
          </views>
407
 
        </register>
408
 
        <register>
409
 
          <address>0x190</address>
410
 
          <offset>0</offset>
411
 
          <size>32</size>
412
 
          <default>0</default>
413
 
          <rwmask>0</rwmask>
414
 
          <mode>R</mode>
415
 
          <name>temperature_sample_period</name>
416
 
        </register>
417
 
        <register>
418
 
          <address>0x1a0</address>
419
 
          <offset>0</offset>
420
 
          <size>32</size>
421
 
          <default>0x64</default>
422
 
          <rwmask>0</rwmask>
423
 
          <mode>RW</mode>
424
 
          <name>ddr_max_frames</name>
425
 
        </register>
426
 
        <register>
427
 
          <address>0x1b0</address>
428
 
          <offset>0</offset>
429
 
          <size>32</size>
430
 
          <default>0</default>
431
 
          <rwmask>0</rwmask>
432
 
          <mode>R</mode>
433
 
          <name>ddr_num_frames</name>
434
 
        </register>
435
 
      </registers>
436
 
    </bank>
437
 
    <bank>
438
 
        <bank_description>
439
 
        <bar>0</bar>
440
 
        <size>0x0200</size>
441
 
        <protocol>default</protocol>
442
 
        <read_address>0x0</read_address>
443
 
        <write_address>0x0</write_address>
444
 
        <word_size>32</word_size>
445
 
        <endianess>little</endianess>
446
 
        <format>0x%lx</format>
447
 
        <name>dma</name>
448
 
        <description>DMA Registers</description>
449
 
        </bank_description>
450
 
    </bank>
451
 
  </banks>
452
 
  <views>
453
 
    <view type="formula">
454
 
      <name>formuu1</name>
455
 
        <unit>C</unit>
456
 
      <read_from_register>(503975./1024000)*@reg - 27315./100</read_from_register>
457
 
      <write_to_register>(@value + 27315./100)*(102400./503975)</write_to_register>
458
 
<description>formula to get real fpga temperature from the fpga_temperature register in decimal</description>
459
 
    </view>
460
 
    <view type="enum">
461
 
      <name>enumm1</name>
462
 
      <enum value="0x100" min="0x2" max="0x300">high</enum>
463
 
      <enum value="0x010">low</enum>
464
 
        <description>enum towards temperatures register</description>
465
 
    </view>
466
 
    <view type="formula">
467
 
      <name>formuu2</name>
468
 
        <unit>C</unit>
469
 
      <read_from_register>((1./4)*(@reg - 1200)) if @freq==0 else ((3./10)*(@reg - 1000))</read_from_register>
470
 
      <write_to_register>4*@value + 1200 if @freq==0 else (10./3)*@value + 1000</write_to_register>
471
 
      <description>formula to get real sensor temperature from the sensor_temperature register in decimal</description>
472
 
    </view>
473
 
    <view type="enum">
474
 
      <name>enumm2</name>
475
 
      <enum value="0x120">high</enum>
476
 
      <enum value="0x010" min="0x00" max="0x020">low</enum>
477
 
           <description>enum towards sensor_temperature register</description>
478
 
    </view>
479
 
    <view type="formula">
480
 
      <name>formuu3</name>
481
 
        <unit>us</unit>  
482
 
      <read_from_register>(@reg+(43./100))*129./(40*1000000)if @freq==0 else (@reg+(43./100))*129./(48*1000000)</read_from_register>
483
 
      <write_to_register>@value/129.*(40*1000000) - 43./100 if @freq==0 else @value/129.*(48*1000000) - 43./100</write_to_register>
484
 
        <description>formula to get real exposure time from the cmosis_exp_time register in decimal</description> 
485
 
    </view>
486
 
    <view type="enum">
487
 
      <name>enumm3</name>
488
 
      <enum  value="0x000">short</enum>
489
 
      <enum  value="0x010">mid</enum>
490
 
      <enum  value="0x100" min="0x0F0">long</enum>
491
 
        <description>enum towards cmosis_exp_register register</description>
492
 
    </view>
493
 
  </views>
 
3
  <bank bar="0" size="128" protocol="software_registers" read_address="0x9010" write_address="0x9000" word_size="8" endianess="little" format="%lu" name="cmosis" description="CMOSIS CMV2000 Registers">
 
4
    <register address="1" offset="0" size="16" default="1088" rwmask="0" mode="RW" name="cmosis_number_lines" description="test"/>
 
5
    <register address="3" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start1"/>
 
6
    <register address="5" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start2"/>
 
7
    <register address="7" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start3"/>
 
8
    <register address="9" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start4"/>
 
9
    <register address="11" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start5"/>
 
10
    <register address="13" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start6"/>
 
11
    <register address="15" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start7"/>
 
12
    <register address="17" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_start8"/>
 
13
    <register address="19" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines1"/>
 
14
    <register address="21" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines2"/>
 
15
    <register address="23" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines3"/>
 
16
    <register address="25" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines4"/>
 
17
    <register address="27" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines5"/>
 
18
    <register address="29" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines6"/>
 
19
    <register address="31" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines7"/>
 
20
    <register address="33" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_number_lines8"/>
 
21
    <register address="35" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_sub_s"/>
 
22
    <register address="37" offset="0" size="16" default="0" rwmask="0" mode="RW" name="cmosis_sub_a"/>
 
23
    <register address="39" offset="0" size="1" default="1" rwmask="0" mode="RW" name="cmosis_color"/>
 
24
    <register address="40" offset="0" size="2" default="0" rwmask="0" mode="RW" name="cmosis_image_flipping"/>
 
25
    <register address="41" offset="0" size="2" default="0" rwmask="0" mode="RW" name="cmosis_exp_flags"/>
 
26
    <register address="42" offset="0" size="24" default="1088" rwmask="0" mode="RW" name="cmosis_exp_time"><view view="formuu3"/><view view="enumm3"/></register>
 
27
    <register address="45" offset="0" size="24" default="1088" rwmask="0" mode="RW" name="cmosis_exp_step"/>
 
28
    <register address="48" offset="0" size="24" default="1" rwmask="0" mode="RW" name="cmosis_exp_kp1"/>
 
29
    <register address="51" offset="0" size="24" default="1" rwmask="0" mode="RW" name="cmosis_exp_kp2"/>
 
30
    <register address="54" offset="0" size="2" default="1" rwmask="0" mode="RW" name="cmosis_nr_slopes"/>
 
31
    <register address="55" offset="0" size="8" default="1" rwmask="0" mode="RW" name="cmosis_exp_seq"/>
 
32
    <register address="56" offset="0" size="24" default="1088" rwmask="0" mode="RW" name="cmosis_exp_time2"/>
 
33
    <register address="59" offset="0" size="24" default="1088" rwmask="0" mode="RW" name="cmosis_exp_step2"/>
 
34
    <register address="68" offset="0" size="2" default="1" rwmask="0" mode="RW" name="cmosis_nr_slopes2"/>
 
35
    <register address="69" offset="0" size="8" default="1" rwmask="0" mode="RW" name="cmosis_exp_seq2"/>
 
36
    <register address="70" offset="0" size="16" default="1" rwmask="0" mode="RW" name="cmosis_number_frames"/>
 
37
    <register address="72" offset="0" size="2" default="0" rwmask="0" mode="RW" name="cmosis_output_mode"/>
 
38
    <register address="78" offset="0" size="12" default="85" rwmask="0" mode="RW" name="cmosis_training_pattern"/>
 
39
    <register address="80" offset="0" size="18" default="0x3FFFF" rwmask="0" mode="RW" name="cmosis_channel_en"/>
 
40
    <register address="82" offset="0" size="3" default="7" rwmask="0" mode="RW" name="cmosis_special_82"/>
 
41
    <register address="89" offset="0" size="8" default="96" rwmask="0" mode="RW" name="cmosis_vlow2"/>
 
42
    <register address="90" offset="0" size="8" default="96" rwmask="0" mode="RW" name="cmosis_vlow3"/>
 
43
    <register address="100" offset="0" size="14" default="16260" rwmask="0" mode="RW" name="cmosis_offset"/>
 
44
    <register address="102" offset="0" size="2" default="0" rwmask="0" mode="RW" name="cmosis_pga"/>
 
45
    <register address="103" offset="0" size="8" default="32" rwmask="0" mode="RW" name="cmosis_adc_gain"/>
 
46
    <register address="111" offset="0" size="1" default="1" rwmask="0" mode="RW" name="cmosis_bit_mode"/>
 
47
    <register address="112" offset="0" size="2" default="0" rwmask="0" mode="RW" name="cmosis_adc_resolution"/>
 
48
    <register address="115" offset="0" size="1" default="1" rwmask="0" mode="RW" name="cmosis_special_115"/>
 
49
  </bank>
 
50
  <bank bar="0" size="0x0200" protocol="software_registers" read_address="0x9000" write_address="0x9000" word_size="32" endianess="little" format="0x%lx" name="fpga" description="IPECamera Registers">
 
51
    <register address="0x00" offset="0" size="32" default="0" rwmask="0" mode="RW" name="spi_conf_input"/>
 
52
    <register address="0x10" offset="0" size="32" default="0" rwmask="0" mode="R" name="spi_conf_output"/>
 
53
    <register address="0x20" offset="0" size="32" default="0" rwmask="0" mode="RW" name="spi_clk_speed"/>
 
54
    <register address="0x30" offset="0" size="32" default="0" rwmask="0" mode="R" name="firmware_info">
 
55
      <field offset="0" size="8" mode="R" name="firmware_version"/>
 
56
      <field offset="8" size="1" mode="R" name="firmware_bitmode"/>
 
57
      <field offset="12" size="2" mode="R" name="adc_resolution"/>
 
58
      <field offset="16" size="2" mode="R" name="output_mode"/>
 
59
    </register>
 
60
    <register address="0x40" offset="0" size="32" default="0" rwmask="0" mode="RW" name="control">
 
61
      <field offset="31" size="1" mode="R" name="freq"/>
 
62
    </register>
 
63
    <register address="0x50" offset="0" size="32" default="0" rwmask="0" mode="R" name="status"/>
 
64
    <register address="0x54" offset="0" size="32" default="0" rwmask="0" mode="R" name="status2"/>
 
65
    <register address="0x58" offset="0" size="32" default="0" rwmask="0" mode="R" name="status3"/>
 
66
    <register address="0x5c" offset="0" size="32" default="0" rwmask="0" mode="R" name="fr_status"/>
 
67
    <register address="0x70" offset="0" size="32" default="0" rwmask="0" mode="R" name="start_address"/>
 
68
    <register address="0x74" offset="0" size="32" default="0" rwmask="0" mode="R" name="end_address"/>
 
69
    <register address="0x78" offset="0" size="32" default="0" rwmask="0" mode="R" name="rd_address"/>
 
70
    <register address="0xa0" offset="0" size="32" default="0" rwmask="0" mode="R" name="fr_param1">
 
71
      <field offset="0" size="10" mode="RW" name="fr_skip_lines"/>
 
72
      <field offset="10" size="11" mode="RW" name="fr_num_lines"/>
 
73
      <field offset="21" size="11" mode="RW" name="fr_start_address"/>
 
74
    </register>
 
75
    <register address="0xb0" offset="0" size="32" default="0" rwmask="all" mode="RW" name="fr_param2">
 
76
      <field offset="0" size="11" mode="RW" name="fr_threshold_start_line"/>
 
77
      <field offset="16" size="10" mode="RW" name="fr_area_lines"/>
 
78
    </register>
 
79
    <register address="0xc0" offset="0" size="32" default="0" rwmask="0" mode="R" name="skiped_lines"/>
 
80
    <register address="0xd0" offset="0" size="32" default="0" rwmask="all" mode="RW" name="fr_thresholds"/>
 
81
    <register address="0xd0" offset="0" size="10" default="0" rwmask="all" mode="RW" name="fr_pixel_thr"/>
 
82
    <register address="0xd0" offset="10" size="11" default="0" rwmask="all" mode="RW" name="fr_num_pixel_thr"/>
 
83
    <register address="0xd0" offset="21" size="11" default="0" rwmask="all" mode="RW" name="fr_num_lines_thr"/>
 
84
    <register address="0x100" offset="0" size="32" default="0" rwmask="0" mode="RW" name="rawdata_pkt_addr"/>
 
85
    <register address="0x110" offset="0" size="32" default="0" rwmask="0" mode="R" name="temperature_info">
 
86
      <field offset="0" size="16" mode="R" name="sensor_temperature"><view view="formuu1"/><view view="formuu2"/><view view="enumm2"/></field>
 
87
      <field offset="16" size="3" mode="R" name="sensor_temperature_alarms"/>
 
88
      <field offset="19" size="10" mode="RW" name="fpga_temperature"><view view="formuu1"/><view view="enumm1"/></field>
 
89
      <field offset="29" size="3" mode="R" name="fpga_temperature_alarms"/>
 
90
    </register>
 
91
    <register address="0x120" offset="0" size="32" default="0" rwmask="0" mode="R" name="num_lines"/>
 
92
    <register address="0x130" offset="0" size="32" default="0" rwmask="0" mode="R" name="start_line"/>
 
93
    <register address="0x140" offset="0" size="32" default="0" rwmask="0" mode="R" name="exp_time"/>
 
94
    <register address="0x150" offset="0" size="32" default="0" rwmask="0" mode="RW" name="motor">
 
95
      <field offset="0" size="5" mode="RW" name="motor_phi"/>
 
96
      <field offset="5" size="5" mode="RW" name="motor_z"/>
 
97
      <field offset="10" size="5" mode="RW" name="motor_y"/>
 
98
      <field offset="15" size="5" mode="RW" name="motor_x"/>
 
99
      <field offset="20" size="8" mode="R" name="adc_gain"/>
 
100
    </register>
 
101
    <register address="0x160" offset="0" size="32" default="0" rwmask="0" mode="R" name="write_status"/>
 
102
    <register address="0x170" offset="0" size="32" default="0" rwmask="0" mode="RW" name="num_triggers"/>
 
103
    <register address="0x180" offset="0" size="32" default="0x280" rwmask="0" mode="RW" name="trigger_period"><view view="enumm2"/></register>
 
104
    <register address="0x190" offset="0" size="32" default="0" rwmask="0" mode="R" name="temperature_sample_period"/>
 
105
    <register address="0x1a0" offset="0" size="32" default="0x64" rwmask="0" mode="RW" name="ddr_max_frames"/>
 
106
    <register address="0x1b0" offset="0" size="32" default="0" rwmask="0" mode="R" name="ddr_num_frames"/>
 
107
  </bank>
 
108
  <bank bar="0" size="0x0200" protocol="software_registers" read_address="0x0" write_address="0x0" word_size="32" endianess="little" format="0x%lx" name="dma" description="DMA Registers"/>
 
109
  <transform name="formuu1" unit="C" read_from_register="(503975./1024000)*$value - 27315./100" write_to_register="($value + 27315./100)*(102400./503975)" description="formula to get real fpga temperature from the fpga_temperature register in decimal"/>
 
110
  <transform name="formuu2" unit="C" read_from_register="((1./4)*($value - 1200)) if $freq==0 else ((3./10)*($value - 1000))" write_to_register="4*$value + 1200 if $freq==0 else (10./3)*$value + 1000" description="formula to get real sensor temperature from the sensor_temperature register in decimal"/>
 
111
  <transform name="formuu3" unit="us" read_from_register="($value+(43./100))*129./(40*1000000)if $freq==0 else ($value+(43./100))*129./(48*1000000)" write_to_register="$value/129.*(40*1000000) - 43./100 if $freq==0 else $value/129.*(48*1000000) - 43./100" description="formula to get real exposure time from the cmosis_exp_time register in decimal"/>
 
112
  <enum name="enumm1" description="enum towards temperatures register">
 
113
    <name name="high" value="0x100" min="0x2" max="0x300"/>
 
114
    <name name="low" value="0x010"/>
 
115
  </enum>
 
116
  <enum name="enumm2" description="enum towards sensor_temperature register">
 
117
    <name name="high" value="0x120"/>
 
118
    <name name="low" value="0x010" min="0x00" max="0x020"/>
 
119
  </enum>
 
120
  <enum name="enumm3" description="enum towards cmosis_exp_register register">
 
121
    <name name="short" value="0x000"/>
 
122
    <name name="mid" value="0x010"/>
 
123
    <name name="long" value="0x100" min="0x0F0"/>
 
124
  </enum>
 
125
  <unit name="C">
 
126
    <transform unit="K" transform="$value+273.15"/>
 
127
    <transform unit="F" transform="$value*(9./5)+32"/>
 
128
  </unit>
 
129
  <unit name="K">
 
130
    <transform unit="C" transform="$value-273.15"/>
 
131
    <transform unit="F" transform="($value-273.15)*(9./5)+32"/>
 
132
  </unit>
 
133
  <unit name="F">
 
134
    <transform unit="C" transform="($value-32)*5./9"/>
 
135
    <transform unit="K" transform="($value+273.15-32)*5./9"/>
 
136
  </unit>
 
137
  <unit name="s">
 
138
    <transform unit="ms" transform="$value*1000"/>
 
139
    <transform unit="us" transform="$value*1000000"/>
 
140
    <transform unit="ns" transform="$value*1000000000"/>
 
141
  </unit>
 
142
  <unit name="ms">
 
143
    <transform unit="s" transform="$value/1000"/>
 
144
    <transform unit="us" transform="$value*1000"/>
 
145
    <transform unit="ns" transform="$value*1000000"/>
 
146
  </unit>
 
147
  <unit name="us">
 
148
    <transform unit="s" transform="$value/1000000"/>
 
149
    <transform unit="ms" transform="$value/1000"/>
 
150
    <transform unit="ns" transform="$value*1000"/>
 
151
  </unit>
 
152
  <unit name="ns">
 
153
    <transform unit="s" transform="$value/1000000000"/>
 
154
    <transform unit="ms" transform="$value/1000000"/>
 
155
    <transform unit="us" transform="$value/1000"/>
 
156
  </unit>
494
157
</model>