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Viewing changes to dma/nwl_engine_buffers.h

  • Committer: Suren A. Chilingaryan
  • Date: 2011-10-26 05:12:31 UTC
  • Revision ID: csa@dside.dyndns.org-20111026051231-5ntkozz31hvjzvb5
Improvements of DMA engine

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Lines of Context:
dma/nwl_engine_buffers.h
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    val = ring_pa + info->head * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
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    nwl_write_register(val, ctx, info->base_addr, REG_SW_NEXT_BD);
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//    nwl_read_register(val, ctx, info->base_addr, 0x18);
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//    usleep(10000);
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//    nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_LAST_BD);
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//    printf("Last BD(Write): %lx %lx\n", ring, val);
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    return 0;
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}
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    struct timeval start, cur;
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    uint32_t status_size, status, control;
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//    usleep(10000);
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    unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring);
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//    status_size = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET);
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//    printf("Status0: %lx\n", status_size);
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    ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
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    gettimeofday(&start, NULL);
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//    printf("Waiting %li\n", info->tail);
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//    nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_LAST_BD);
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//    printf("Last BD(Read): %lx %lx\n", ring, val);
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    do {
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        status_size = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET);
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        status = status_size & DMA_BD_STATUS_MASK;
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//      printf("%i: %lx\n", info->tail, status_size);
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        if (status & DMA_BD_ERROR_MASK) {
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            pcilib_error("NWL DMA Engine reported error in ring descriptor");
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            return (size_t)-1;
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        if (status & DMA_BD_COMP_MASK) {
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            if (status & DMA_BD_EOP_MASK) *eop = 1;
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            else *eop = 0;
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            *size = status_size & DMA_BD_BUFL_MASK;
 
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/*          
 
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            if (mrd) {
 
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                if ((info->tail + 1) == info->ring_size) ring -= info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
 
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                else ring += PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
 
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                *mrd = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET)&DMA_BD_COMP_MASK;
 
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            }
 
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*/
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//          printf("Status: %lx\n", status_size);
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            return info->tail;
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        }
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        gettimeofday(&cur, NULL);
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    } while ((timeout == PCILIB_TIMEOUT_INFINITE)||(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < timeout));
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//    printf("Final status: %lx\n", status_size);
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    return (size_t)-1;
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}
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static int dma_nwl_is_overflown(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info) {
 
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    uint32_t status;
 
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    unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring);
 
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    if (info->tail > 0) ring += (info->tail - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
 
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    else ring += (info->ring_size - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
 
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    status = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET);
 
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    return status&DMA_BD_COMP_MASK?1:0;
 
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}
 
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static int dma_nwl_return_buffer(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info) {
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    uint32_t val;
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    size_t bufsz = pcilib_kmem_get_block_size(ctx->pcilib, info->pages, info->tail);
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    ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
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//    printf("Returning: %i\n", info->tail);
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#ifdef NWL_GENERATE_DMA_IRQ    
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    NWL_RING_SET(ring, DMA_BD_BUFL_CTRL_OFFSET, bufsz | DMA_BD_INT_ERROR_MASK | DMA_BD_INT_COMP_MASK);
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    val = ring_pa + info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
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    nwl_write_register(val, ctx, info->base_addr, REG_SW_NEXT_BD);
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//    nwl_read_register(val, ctx, info->base_addr, 0x18);
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    info->tail++;
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    if (info->tail == info->ring_size) info->tail = 0;
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}
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int dma_nwl_get_status(pcilib_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers) {
 
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int dma_nwl_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers) {
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    size_t i;
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    uint32_t bstatus;
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    return 0;
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}
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/*
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    unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring);
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//    status_size = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET);
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//    printf("Status0: %lx\n", status_size);
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    ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE;
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    gettimeofday(&start, NULL);
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//    printf("Waiting %li\n", info->tail);
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//    nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_LAST_BD);
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//    printf("Last BD(Read): %lx %lx\n", ring, val);
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    do {
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        status_size = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET);
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        status = status_size & DMA_BD_STATUS_MASK;
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//      printf("%i: %lx\n", info->tail, status_size);
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        if (status & DMA_BD_ERROR_MASK) {
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            pcilib_error("NWL DMA Engine reported error in ring descriptor");
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            return (size_t)-1;
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        }       
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        if (status & DMA_BD_COMP_MASK) {
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            if (status & DMA_BD_EOP_MASK) *eop = 1;
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            else *eop = 0;
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            *size = status_size & DMA_BD_BUFL_MASK;
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//          printf("Status: %lx\n", status_size);
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            return info->tail;
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        }
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        usleep(10);
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        gettimeofday(&cur, NULL);
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    } while ((timeout == PCILIB_TIMEOUT_INFINITE)||(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < timeout));
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*/
 
 
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