132
139
{"free-kernel-memory", required_argument, 0, OPT_FREE_KMEM },
133
140
{"quiete", no_argument, 0, OPT_QUIETE },
134
141
{"force", no_argument, 0, OPT_FORCE },
142
{"multipacket", no_argument, 0, OPT_MULTIPACKET },
143
{"wait", no_argument, 0, OPT_WAIT },
135
144
{"help", no_argument, 0, OPT_HELP },
194
203
" -o <file> - Append output to file (default: stdout)\n"
195
204
" -t <timeout> - Timeout in microseconds\n"
207
" --multipacket - Read multiple packets\n"
208
" --wait - Wait until data arrives\n"
197
210
" Information:\n"
198
211
" -q - Quiete mode (suppress warnings)\n"
395
408
for (size = min_size; size <= max_size; size *= 4) {
396
mbs_in = pcilib_benchmark_dma(handle, dma, addr, size, BENCHMARK_ITERATIONS, PCILIB_DMA_FROM_DEVICE);
397
mbs_out = pcilib_benchmark_dma(handle, dma, addr, size, BENCHMARK_ITERATIONS, PCILIB_DMA_TO_DEVICE);
409
mbs_in = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_FROM_DEVICE);
410
mbs_out = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_TO_DEVICE);
398
411
mbs = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_BIDIRECTIONAL);
399
412
err = pcilib_wait_irq(handle, 0, 0, &irqs);
400
413
if (err) irqs = 0;
572
585
#define pci2host16(endianess, value) endianess?
575
int ReadData(pcilib_t *handle, ACCESS_MODE mode, pcilib_dma_engine_addr_t dma, pcilib_bar_t bar, uintptr_t addr, size_t n, access_t access, int endianess, FILE *o) {
594
} DMACallbackContext;
596
static int DMACallback(void *arg, pcilib_dma_flags_t flags, size_t bufsize, void *buf) {
597
DMACallbackContext *ctx = (DMACallbackContext*)arg;
599
if ((ctx->pos + bufsize > ctx->size)||(!ctx->data)) {
601
ctx->data = realloc(ctx->data, ctx->size);
603
Error("Allocation of %i bytes of memory have failed", ctx->size);
608
memcpy(ctx->data + ctx->pos, buf, bufsize);
611
if (flags & PCILIB_DMA_FLAG_EOP) return 0;
617
int ReadData(pcilib_t *handle, ACCESS_MODE mode, FLAGS flags, pcilib_dma_engine_addr_t dma, pcilib_bar_t bar, uintptr_t addr, size_t n, access_t access, int endianess, size_t timeout, FILE *o) {
579
621
int size = n * abs(access);
580
622
int block_width, blocks_per_line;
581
623
int numbers_per_block, numbers_per_line;
582
624
pcilib_dma_engine_t dmaid;
625
pcilib_dma_flags_t dma_flags = 0;
584
627
numbers_per_block = BLOCK_SIZE / access;
588
631
if ((blocks_per_line > 1)&&(blocks_per_line % 2)) --blocks_per_line;
589
632
numbers_per_line = blocks_per_line * numbers_per_block;
591
// buf = alloca(size);
592
err = posix_memalign( (void**)&buf, 256, size );
593
if ((err)||(!buf)) Error("Allocation of %i bytes of memory have failed", size);
636
if (!buf) Error("Allocation of %i bytes of memory have failed", size);
643
if (timeout == (size_t)-1) timeout = PCILIB_DMA_TIMEOUT;
597
645
dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_FROM_DEVICE, dma);
598
646
if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("Invalid DMA engine (%lu) is specified", dma);
599
err = pcilib_read_dma(handle, dmaid, addr, size, buf, &ret);
600
if ((err)||(ret <= 0)) Error("No data is returned by DMA engine");
602
n = ret / abs(access);
648
if (flags&FLAG_MULTIPACKET) dma_flags |= PCILIB_DMA_FLAG_MULTIPACKET;
649
if (flags&FLAG_WAIT) dma_flags |= PCILIB_DMA_FLAG_WAIT;
652
err = pcilib_read_dma_custom(handle, dmaid, addr, size, dma_flags, timeout, buf, &bytes);
653
if (err) Error("Error (%i) is reported by DMA engine", err);
655
dma_flags |= PCILIB_DMA_FLAG_IGNORE_ERRORS;
657
size = 2048; bytes = 0;
660
buf = realloc(buf, size);
661
err = pcilib_read_dma_custom(handle, dmaid, addr, size - bytes, dma_flags, timeout, buf + bytes, &ret);
664
if ((!err)&&(flags&FLAG_MULTIPACKET)) {
665
err = PCILIB_ERROR_TOOBIG;
666
if ((flags&FLAG_WAIT)==0) timeout = 0;
668
} while (err == PCILIB_ERROR_TOOBIG);
670
if (bytes <= 0) Error("No data is returned by DMA engine");
672
n = bytes / abs(access);
605
675
case ACCESS_FIFO:
818
891
if ((read_back)&&(memcmp(buf, check, size))) {
819
892
printf("Write failed: the data written and read differ, the foolowing is read back:\n");
820
893
if (endianess) pcilib_swap(check, check, abs(access), n);
821
ReadData(handle, mode, dma, bar, addr, n, access, endianess, NULL);
894
ReadData(handle, mode, 0, dma, bar, addr, n, access, endianess, (size_t)-1, NULL);
829
904
int WriteRegisterRange(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, uintptr_t addr, size_t n, char ** data) {
1412
1489
pcilib_model_t model = PCILIB_MODEL_DETECT;
1413
1490
pcilib_model_description_t *model_info;
1414
1491
MODE mode = MODE_INVALID;
1415
1493
const char *type = NULL;
1416
1494
ACCESS_MODE amode = ACCESS_BAR;
1417
1495
const char *fpga_device = DEFAULT_FPGA_DEVICE;
1645
1723
case OPT_TIMEOUT:
1646
1724
if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &timeout) != 1))
1647
1725
Usage(argc, argv, "Invalid timeout is specified (%s)", optarg);
1649
1728
case OPT_OUTPUT:
1650
1729
output = optarg;
1652
1731
case OPT_ITERATIONS:
1653
1732
if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &iterations) != 1))
1654
1733
Usage(argc, argv, "Invalid number of iterations is specified (%s)", optarg);
1657
1735
case OPT_QUIETE:
1823
1907
Benchmark(handle, amode, dma, bar, start, size_set?size:0, access, iterations);
1825
1909
case MODE_READ:
1826
if ((addr)||(amode == ACCESS_DMA)) {
1827
ReadData(handle, amode, dma, bar, start, size, access, endianess, ofile);
1910
if (amode == ACCESS_DMA) {
1911
ReadData(handle, amode, flags, dma, bar, start, size_set?size:0, access, endianess, timeout_set?timeout:(size_t)-1, ofile);
1913
ReadData(handle, amode, flags, dma, bar, start, size, access, endianess, (size_t)-1, ofile);
1829
1915
Error("Address to read is not specified");