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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-07-24 13:09:23 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-07-24 13:09:23 +0200 |
| commit | fb42f24213a7aaecbd631e61fb432ef04742d2ce (patch) | |
| tree | c689e861d9776e42bf51dd02883298249c23ac42 /dma/ipe.h | |
| parent | e2515f6e1a7b17addda4c558a0a6ca05b4ec6e55 (diff) | |
| download | pcitool-fb42f24213a7aaecbd631e61fb432ef04742d2ce.tar.gz pcitool-fb42f24213a7aaecbd631e61fb432ef04742d2ce.tar.bz2 pcitool-fb42f24213a7aaecbd631e61fb432ef04742d2ce.tar.xz pcitool-fb42f24213a7aaecbd631e61fb432ef04742d2ce.zip | |
Use 64-bit addressing in IPEDMA only for gen3 boards or if enforced
Diffstat (limited to 'dma/ipe.h')
| -rw-r--r-- | dma/ipe.h | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -65,6 +65,7 @@ static const pcilib_register_description_t ipe_dma_registers[] = { {0x000C, 24, 8, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr", "Upper address for 64 bit memory addressing"}, {0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count", "Write DMA TLP Count"}, {0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern", "DMA generator data pattern"}, + {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "pcie_gen", "PCIe version 2/3 depending on the used XILINX core"}, {0x0028, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf", "MWR Performance"}, {0x003C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width", "Negotiated and max width of PCIe Link"}, {0x003C, 0, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width", "Max link width"}, |