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authorSuren A. Chilingaryan <csa@suren.me>2015-07-24 13:09:23 +0200
committerSuren A. Chilingaryan <csa@suren.me>2015-07-24 13:09:23 +0200
commitfb42f24213a7aaecbd631e61fb432ef04742d2ce (patch)
treec689e861d9776e42bf51dd02883298249c23ac42
parente2515f6e1a7b17addda4c558a0a6ca05b4ec6e55 (diff)
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Use 64-bit addressing in IPEDMA only for gen3 boards or if enforced
-rw-r--r--dma/ipe.c18
-rw-r--r--dma/ipe.h1
-rw-r--r--dma/ipe_private.h7
3 files changed, 16 insertions, 10 deletions
diff --git a/dma/ipe.c b/dma/ipe.c
index 953de09..814bc77 100644
--- a/dma/ipe.c
+++ b/dma/ipe.c
@@ -22,8 +22,8 @@
pcilib_dma_context_t *dma_ipe_init(pcilib_t *pcilib, const char *model, const void *arg) {
-// int err = 0;
-
+ pcilib_register_value_t value;
+
const pcilib_model_description_t *model_info = pcilib_get_model_description(pcilib);
ipe_dma_t *ctx = malloc(sizeof(ipe_dma_t));
@@ -32,11 +32,6 @@ pcilib_dma_context_t *dma_ipe_init(pcilib_t *pcilib, const char *model, const vo
memset(ctx, 0, sizeof(ipe_dma_t));
ctx->dmactx.pcilib = pcilib;
-#ifdef IPEDMA_64BIT_MODE
- // Always supported and we need to use it
- ctx->mode64 = 1;
-#endif /* IPEDMA_64BIT_MODE */
-
pcilib_register_bank_t dma_bank = pcilib_find_register_bank_by_addr(pcilib, PCILIB_REGISTER_BANK_DMA);
if (dma_bank == PCILIB_REGISTER_BANK_INVALID) {
@@ -47,6 +42,15 @@ pcilib_dma_context_t *dma_ipe_init(pcilib_t *pcilib, const char *model, const vo
ctx->dma_bank = model_info->banks + dma_bank;
ctx->base_addr = pcilib_resolve_register_address(pcilib, ctx->dma_bank->bar, ctx->dma_bank->read_addr);
+
+#ifdef IPEDMA_ENFORCE_64BIT_MODE
+ ctx->mode64 = 1;
+#else /* IPEDMA_ENFORCE_64BIT_MODE */
+ // According to Lorenzo, some gen2 boards have problems with 64-bit addressing. Therefore, we only enable it for gen3 boards unless enforced
+ RD(IPEDMA_REG_PCIE_GEN, value);
+ if (value > 2) ctx->mode64 = 1;
+ else ctx->mode64 = 0;
+#endif /* IPEDMA_ENFORCE_64BIT_MODE */
}
return (pcilib_dma_context_t*)ctx;
diff --git a/dma/ipe.h b/dma/ipe.h
index 5640606..76be4f4 100644
--- a/dma/ipe.h
+++ b/dma/ipe.h
@@ -65,6 +65,7 @@ static const pcilib_register_description_t ipe_dma_registers[] = {
{0x000C, 24, 8, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr", "Upper address for 64 bit memory addressing"},
{0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count", "Write DMA TLP Count"},
{0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern", "DMA generator data pattern"},
+ {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "pcie_gen", "PCIe version 2/3 depending on the used XILINX core"},
{0x0028, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf", "MWR Performance"},
{0x003C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width", "Negotiated and max width of PCIe Link"},
{0x003C, 0, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width", "Max link width"},
diff --git a/dma/ipe_private.h b/dma/ipe_private.h
index 249286d..937e202 100644
--- a/dma/ipe_private.h
+++ b/dma/ipe_private.h
@@ -3,12 +3,12 @@
#include "dma.h"
-#define IPEDMA_64BIT_MODE 1 /**< 64-bit mode addressing is required to support PCIe gen3 */
+//#define IPEDMA_ENFORCE_64BIT_MODE 1 /**< enforce 64-bit mode addressing (otherwise it is used only if register 0x18 specifies PCIe gen3 as required by DMA engine) */
#define IPEDMA_CORES 1
#define IPEDMA_MAX_TLP_SIZE 256 /**< Defines maximum TLP in bytes supported by device */
-//#define IPEDMA_TLP_SIZE 128 /**< If set, enforces the specified TLP size */
+//#define IPEDMA_TLP_SIZE 128 /**< If set, enforces the specified TLP size */
-#define IPEDMA_STREAMING_MODE /**< Enables streaming DMA operation mode instead of ring-buffer, the page is written once and forgotten and need to be pushed in queue again */
+//#define IPEDMA_STREAMING_MODE /**< Enables streaming DMA operation mode instead of ring-buffer, the page is written once and forgotten and need to be pushed in queue again */
#define IPEDMA_STREAMING_CHECKS /**< Enables status checks in streaming mode (it will cause performance penalty) */
#define IPEDMA_PAGE_SIZE 4096
#define IPEDMA_DMA_PAGES 1024 /**< number of DMA pages in the ring buffer to allocate */
@@ -31,6 +31,7 @@
#define IPEDMA_REG_CONTROL 0x04
#define IPEDMA_REG_TLP_SIZE 0x0C
#define IPEDMA_REG_TLP_COUNT 0x10
+#define IPEDMA_REG_PCIE_GEN 0x18
#define IPEDMA_REG_PAGE_ADDR 0x50
#define IPEDMA_REG_UPDATE_ADDR 0x54
#define IPEDMA_REG_LAST_READ 0x58 /**< In streaming mode, we can use it freely to track current status */