/alps/pcitool

To get this branch, use:
bzr branch http://suren.me/webbzr/alps/pcitool

« back to all changes in this revision

Viewing changes to ipecamera.h

  • Committer: Suren A. Chilingaryan
  • Date: 2011-03-09 15:55:27 UTC
  • mto: This revision was merged to the branch mainline in revision 8.
  • Revision ID: csa@dside.dyndns.org-20110309155527-7ui77xsz2f7ms0b8
Support for FPGA registers

Show diffs side-by-side

added added

removed removed

Lines of Context:
ipecamera.h
9
9
#define IPECAMERA_REGISTER_WRITE (IPECAMERA_REGISTER_SPACE + 0)
10
10
#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_WRITE + 4)
11
11
 
12
 
 
13
12
#ifdef _IPECAMERA_C
14
13
pcilib_register_bank_description_t ipecamera_register_banks[] = {
15
 
    { PCILIB_REGISTER_BANK0, 128, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE,  PCILIB_BIG_ENDIAN, 8, PCILIB_LITTLE_ENDIAN, "cmosis", "CMOSIS CMV2000 Registers" },
16
 
    { 0, 0, 0, 0, 0, 0, NULL, NULL }
 
14
    { PCILIB_REGISTER_BANK0, 128, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, PCILIB_BIG_ENDIAN, 8, PCILIB_LITTLE_ENDIAN, "cmosis", "CMOSIS CMV2000 Registers" },
 
15
    { PCILIB_REGISTER_BANK1, 64, PCILIB_DEFAULT_PROTOCOL, IPECAMERA_REGISTER_SPACE, IPECAMERA_REGISTER_SPACE, PCILIB_BIG_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "fpga", "IPECamera Registers" },
 
16
    { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL }
17
17
};
18
18
 
19
19
pcilib_register_description_t ipecamera_registers[] = {
61
61
{111,   1,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "bit_mode", ""},
62
62
{112,   2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "adc_resolution", ""},
63
63
{126,   16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "temp", ""},
 
64
{0,     32,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
 
65
{1,     32,     0,      PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
 
66
{2,     32,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
 
67
{3,     32,     0,      PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "firmware_version", ""},
 
68
{6,     16,     0,      PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "cmosis_temperature", ""},
 
69
{7,     32,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "temperature_sample_timing", ""},
64
70
{0,     0,      0,      0,                  0,                     NULL, NULL}
65
71
};
66
72
 
74
80
extern pcilib_register_range_t ipecamera_register_ranges[];
75
81
#endif 
76
82
 
77
 
 
78
83
int ipecamera_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, uint8_t bits, pcilib_register_value_t *value);
79
84
int ipecamera_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, uint8_t bits, pcilib_register_value_t value);
80
85