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- Committer: Suren A. Chilingaryan
- Date: 2015-09-10 03:08:04 UTC
- mfrom: (277.2.17 test_xml)
- Revision ID: csa@suren.me-20150910030804-djti3wcmk4yubhp7
Initial integration of XML support
- files added:
- pcilib/xml.c
- xml
- xml/test
- files modified:
- CMakeLists.txt
added
removed
xml/test/camera.xml
1
<?xml version="1.0" encoding="ISO-8859-1"?>
2
<model xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
3
<banks>
4
<bank>
5
<bank_description>
6
<bar>0</bar>
7
<size>0x0200</size>
8
<protocol>default</protocol>
9
<read_address>0x9000</read_address>
10
<write_address>0x9000</write_address>
11
<word_size>32</word_size>
12
<endianess>little</endianess>
13
<format>0x%lx</format>
14
<name>fpga</name>
15
<description>IPECamera Registers</description>
16
</bank_description>
17
<registers>
18
<register>
19
<address>0x00</address>
20
<offset>0</offset>
21
<size>32</size>
22
<default>0</default>
23
<rwmask>0</rwmask>
24
<mode>RW</mode>
25
<name>spi_conf_input</name>
26
</register>
27
<register>
28
<address>0x10</address>
29
<offset>0</offset>
30
<size>32</size>
31
<default>0</default>
32
<rwmask>0</rwmask>
33
<mode>R</mode>
34
<name>spi_conf_output</name>
35
</register>
36
<register>
37
<address>0x20</address>
38
<offset>0</offset>
39
<size>32</size>
40
<default>0</default>
41
<rwmask>0</rwmask>
42
<mode>RW</mode>
43
<name>spi_clk_speed</name>
44
</register>
45
<register>
46
<address>0x30</address>
47
<offset>0</offset>
48
<size>32</size>
49
<default>0</default>
50
<rwmask>0</rwmask>
51
<mode>R</mode>
52
<name>firmware_info</name>
53
<registers_bits>
54
<register_bits>
55
<offset>0</offset>
56
<size>8</size>
57
<mode>R</mode>
58
<name>firmware_version</name>
59
</register_bits>
60
<register_bits>
61
<offset>8</offset>
62
<size>1</size>
63
<mode>R</mode>
64
<name>firmware_bitmode</name>
65
</register_bits>
66
<register_bits>
67
<offset>12</offset>
68
<size>2</size>
69
<mode>R</mode>
70
<name>adc_resolution</name>
71
</register_bits>
72
<register_bits>
73
<offset>16</offset>
74
<size>2</size>
75
<mode>R</mode>
76
<name>output_mode</name>
77
</register_bits>
78
</registers_bits>
79
</register>
80
<register>
81
<address>0x40</address>
82
<offset>0</offset>
83
<size>32</size>
84
<default>0</default>
85
<rwmask>0</rwmask>
86
<mode>RW</mode>
87
<name>control</name>
88
<registers_bits>
89
<register_bits>
90
<offset>31</offset>
91
<size>1</size>
92
<mode>R</mode>
93
<name>freq</name>
94
</register_bits>
95
</registers_bits>
96
</register>
97
<register>
98
<address>0x50</address>
99
<offset>0</offset>
100
<size>32</size>
101
<default>0</default>
102
<rwmask>0</rwmask>
103
<mode>R</mode>
104
<name>status</name>
105
</register>
106
<register>
107
<address>0x54</address>
108
<offset>0</offset>
109
<size>32</size>
110
<default>0</default>
111
<rwmask>0</rwmask>
112
<mode>R</mode>
113
<name>status2</name>
114
</register>
115
<register>
116
<address>0x58</address>
117
<offset>0</offset>
118
<size>32</size>
119
<default>0</default>
120
<rwmask>0</rwmask>
121
<mode>R</mode>
122
<name>status3</name>
123
</register>
124
<register>
125
<address>0x5c</address>
126
<offset>0</offset>
127
<size>32</size>
128
<default>0</default>
129
<rwmask>0</rwmask>
130
<mode>R</mode>
131
<name>fr_status</name>
132
</register>
133
<register>
134
<address>0x70</address>
135
<offset>0</offset>
136
<size>32</size>
137
<default>0</default>
138
<rwmask>0</rwmask>
139
<mode>R</mode>
140
<name>start_address</name>
141
</register>
142
<register>
143
<address>0x74</address>
144
<offset>0</offset>
145
<size>32</size>
146
<default>0</default>
147
<rwmask>0</rwmask>
148
<mode>R</mode>
149
<name>end_address</name>
150
</register>
151
<register>
152
<address>0x78</address>
153
<offset>0</offset>
154
<size>32</size>
155
<default>0</default>
156
<rwmask>0</rwmask>
157
<mode>R</mode>
158
<name>rd_address</name>
159
</register>
160
<register>
161
<address>0xa0</address>
162
<offset>0</offset>
163
<size>32</size>
164
<default>0</default>
165
<rwmask>0</rwmask>
166
<mode>R</mode>
167
<name>fr_param1</name>
168
<registers_bits>
169
<register_bits>
170
<offset>0</offset>
171
<size>10</size>
172
<mode>RW</mode>
173
<name>fr_skip_lines</name>
174
</register_bits>
175
<register_bits>
176
<offset>10</offset>
177
<size>11</size>
178
<mode>RW</mode>
179
<name>fr_num_lines</name>
180
</register_bits>
181
<register_bits>
182
<offset>21</offset>
183
<size>11</size>
184
<mode>RW</mode>
185
<name>fr_start_address</name>
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</register_bits>
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</registers_bits>
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</register>
189
<register>
190
<address>0xb0</address>
191
<offset>0</offset>
192
<size>32</size>
193
<default>0</default>
194
<rwmask>all</rwmask>
195
<mode>RW</mode>
196
<name>fr_param2</name>
197
<registers_bits>
198
<register_bits>
199
<offset>0</offset>
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<size>11</size>
201
<mode>RW</mode>
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<name>fr_threshold_start_line</name>
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</register_bits>
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<register_bits>
205
<offset>16</offset>
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<size>10</size>
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<mode>RW</mode>
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<name>fr_area_lines</name>
209
</register_bits>
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</registers_bits>
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</register>
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<register>
213
<address>0xc0</address>
214
<offset>0</offset>
215
<size>32</size>
216
<default>0</default>
217
<rwmask>0</rwmask>
218
<mode>R</mode>
219
<name>skiped_lines</name>
220
</register>
221
<register>
222
<address>0xd0</address>
223
<offset>0</offset>
224
<size>32</size>
225
<default>0</default>
226
<rwmask>all</rwmask>
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<mode>RW</mode>
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<name>fr_thresholds</name>
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</register>
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<register>
231
<address>0xd0</address>
232
<offset>0</offset>
233
<size>10</size>
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<default>0</default>
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<rwmask>all</rwmask>
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<mode>RW</mode>
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<name>fr_pixel_thr</name>
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</register>
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<register>
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<address>0xd0</address>
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<offset>10</offset>
242
<size>11</size>
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<default>0</default>
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<rwmask>all</rwmask>
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<mode>RW</mode>
246
<name>fr_num_pixel_thr</name>
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</register>
248
<register>
249
<address>0xd0</address>
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<offset>21</offset>
251
<size>11</size>
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<default>0</default>
253
<rwmask>all</rwmask>
254
<mode>RW</mode>
255
<name>fr_num_lines_thr</name>
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</register>
257
<register>
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<address>0x100</address>
259
<offset>0</offset>
260
<size>32</size>
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<default>0</default>
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<rwmask>0</rwmask>
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<mode>RW</mode>
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<name>rawdata_pkt_addr</name>
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</register>
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<register>
267
<address>0x110</address>
268
<offset>0</offset>
269
<size>32</size>
270
<default>0</default>
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<rwmask>0</rwmask>
272
<mode>R</mode>
273
<name>temperature_info</name>
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<registers_bits>
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<register_bits>
276
<offset>0</offset>
277
<size>16</size>
278
<mode>R</mode>
279
<name>sensor_temperature</name>
280
<views>
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<view>formuu1</view>
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<view>formuu2</view>
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<view>enumm2</view>
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</views>
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</register_bits>
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<register_bits>
287
<offset>16</offset>
288
<size>3</size>
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<mode>R</mode>
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<name>sensor_temperature_alarms</name>
291
</register_bits>
292
<register_bits>
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<offset>19</offset>
294
<size>10</size>
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<mode>RW</mode>
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<name>fpga_temperature</name>
297
<views>
298
<view>formuu1</view>
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<view>enumm1</view>
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</views>
301
</register_bits>
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<register_bits>
303
<offset>29</offset>
304
<size>3</size>
305
<mode>R</mode>
306
<name>fpga_temperature_alarms</name>
307
</register_bits>
308
</registers_bits>
309
</register>
310
<register>
311
<address>0x120</address>
312
<offset>0</offset>
313
<size>32</size>
314
<default>0</default>
315
<rwmask>0</rwmask>
316
<mode>R</mode>
317
<name>num_lines</name>
318
</register>
319
<register>
320
<address>0x130</address>
321
<offset>0</offset>
322
<size>32</size>
323
<default>0</default>
324
<rwmask>0</rwmask>
325
<mode>R</mode>
326
<name>start_line</name>
327
</register>
328
<register>
329
<address>0x140</address>
330
<offset>0</offset>
331
<size>32</size>
332
<default>0</default>
333
<rwmask>0</rwmask>
334
<mode>R</mode>
335
<name>exp_time</name>
336
</register>
337
<register>
338
<address>0x150</address>
339
<offset>0</offset>
340
<size>32</size>
341
<default>0</default>
342
<rwmask>0</rwmask>
343
<mode>RW</mode>
344
<name>motor</name>
345
<registers_bits>
346
<register_bits>
347
<offset>0</offset>
348
<size>5</size>
349
<mode>RW</mode>
350
<name>motor_phi</name>
351
</register_bits>
352
<register_bits>
353
<offset>5</offset>
354
<size>5</size>
355
<mode>RW</mode>
356
<name>motor_z</name>
357
</register_bits>
358
<register_bits>
359
<offset>10</offset>
360
<size>5</size>
361
<mode>RW</mode>
362
<name>motor_y</name>
363
</register_bits>
364
<register_bits>
365
<offset>15</offset>
366
<size>5</size>
367
<mode>RW</mode>
368
<name>motor_x</name>
369
</register_bits>
370
<register_bits>
371
<offset>20</offset>
372
<size>8</size>
373
<mode>R</mode>
374
<name>adc_gain</name>
375
</register_bits>
376
</registers_bits>
377
</register>
378
<register>
379
<address>0x160</address>
380
<offset>0</offset>
381
<size>32</size>
382
<default>0</default>
383
<rwmask>0</rwmask>
384
<mode>R</mode>
385
<name>write_status</name>
386
</register>
387
<register>
388
<address>0x170</address>
389
<offset>0</offset>
390
<size>32</size>
391
<default>0</default>
392
<rwmask>0</rwmask>
393
<mode>RW</mode>
394
<name>num_triggers</name>
395
</register>
396
<register>
397
<address>0x180</address>
398
<offset>0</offset>
399
<size>32</size>
400
<default>0x280</default>
401
<rwmask>0</rwmask>
402
<mode>RW</mode>
403
<name>trigger_period</name>
404
<views>
405
<view>enumm2</view>
406
</views>
407
</register>
408
<register>
409
<address>0x190</address>
410
<offset>0</offset>
411
<size>32</size>
412
<default>0</default>
413
<rwmask>0</rwmask>
414
<mode>R</mode>
415
<name>temperature_sample_period</name>
416
</register>
417
<register>
418
<address>0x1a0</address>
419
<offset>0</offset>
420
<size>32</size>
421
<default>0x64</default>
422
<rwmask>0</rwmask>
423
<mode>RW</mode>
424
<name>ddr_max_frames</name>
425
</register>
426
<register>
427
<address>0x1b0</address>
428
<offset>0</offset>
429
<size>32</size>
430
<default>0</default>
431
<rwmask>0</rwmask>
432
<mode>R</mode>
433
<name>ddr_num_frames</name>
434
</register>
435
</registers>
436
</bank>
437
<bank>
438
<bank_description>
439
<bar>0</bar>
440
<size>0x0200</size>
441
<protocol>default</protocol>
442
<read_address>0x0</read_address>
443
<write_address>0x0</write_address>
444
<word_size>32</word_size>
445
<endianess>little</endianess>
446
<format>0x%lx</format>
447
<name>dma</name>
448
<description>DMA Registers</description>
449
</bank_description>
450
</bank>
451
</banks>
452
<views>
453
<view type="formula">
454
<name>formuu1</name>
455
<unit>C</unit>
456
<read_from_register>(503975./1024000)*@reg - 27315./100</read_from_register>
457
<write_to_register>(@value + 27315./100)*(102400./503975)</write_to_register>
458
<description>formula to get real fpga temperature from the fpga_temperature register in decimal</description>
459
</view>
460
<view type="enum">
461
<name>enumm1</name>
462
<enum value="0x100" min="0x2" max="0x300">high</enum>
463
<enum value="0x010">low</enum>
464
<description>enum towards temperatures register</description>
465
</view>
466
<view type="formula">
467
<name>formuu2</name>
468
<unit>C</unit>
469
<read_from_register>((1./4)*(@reg - 1200)) if @freq==0 else ((3./10)*(@reg - 1000))</read_from_register>
470
<write_to_register>4*@value + 1200 if @freq==0 else (10./3)*@value + 1000</write_to_register>
471
<description>formula to get real sensor temperature from the sensor_temperature register in decimal</description>
472
</view>
473
<view type="enum">
474
<name>enumm2</name>
475
<enum value="0x120">high</enum>
476
<enum value="0x010" min="0x00" max="0x020">low</enum>
477
<description>enum towards sensor_temperature register</description>
478
</view>
479
<view type="formula">
480
<name>formuu3</name>
481
<unit>us</unit>
482
<read_from_register>(@reg+(43./100))*129./(40*1000000)if @freq==0 else (@reg+(43./100))*129./(48*1000000)</read_from_register>
483
<write_to_register>@value/129.*(40*1000000) - 43./100 if @freq==0 else @value/129.*(48*1000000) - 43./100</write_to_register>
484
<description>formula to get real exposure time from the cmosis_exp_time register in decimal</description>
485
</view>
486
<view type="enum">
487
<name>enumm3</name>
488
<enum value="0x000">short</enum>
489
<enum value="0x010">mid</enum>
490
<enum value="0x100" min="0x0F0">long</enum>
491
<description>enum towards cmosis_exp_register register</description>
492
</view>
493
</views>
494
</model>
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