/alps/pcitool

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Viewing changes to dma/nwl_engine.c

  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-26 23:54:44 UTC
  • Revision ID: csa@suren.me-20150426235444-l9kvuvvfb2ovg8h1
Further adjustments to get ready for independent event plugins

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Lines of Context:
dma/nwl_engine.c
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        do {
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            nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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            gettimeofday(&cur, NULL);
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        } while ((val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT));
 
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        } while ((val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT));
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        if (val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET)) {
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            pcilib_error("Timeout during reset of DMA engine %i", ectx->desc->addr);
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        do {
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            nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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            gettimeofday(&cur, NULL);
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        } while ((val & DMA_ENG_RESET)&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT));
 
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        } while ((val & DMA_ENG_RESET)&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT));
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        if (val & DMA_ENG_RESET) {
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            pcilib_error("Timeout during reset of DMA engine %i", ectx->desc->addr);
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        do {
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            nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS);
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            gettimeofday(&cur, NULL);
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        } while ((val & (DMA_ENG_RUNNING))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT));
 
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        } while ((val & (DMA_ENG_RUNNING))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT));
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        if (ectx->ring) {
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            ring_pa = pcilib_kmem_get_pa(ctx->dmactx.pcilib, ectx->ring);