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#define PCILIB_DMA_BUFFER_INVALID ((size_t)-1)
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int used; /**< Indicates if buffer has unread data or empty and ready for DMA */
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int error; /**< Indicates if data is complete and correctly transfered or some error occured during the DMA transfer */
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int first; /**< Indicates the first buffer of the packet */
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int last; /**< Indicates the last buffer of the packet */
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size_t size; /**< Indicates number of bytes actually written to the buffer */
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} pcilib_dma_buffer_status_t;
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size_t ring_size, buffer_size;
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size_t ring_head, ring_tail;
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int started; /**< Informs if the engine is currently started or not */
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size_t ring_size, buffer_size; /**< The number of allocated DMA buffers and size of each buffer in bytes */
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size_t ring_head, ring_tail; /**< The first and the last buffer containing the data */
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} pcilib_dma_engine_status_t;
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PCILIB_DMA_TYPE_BLOCK,
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PCILIB_DMA_TYPE_PACKET,
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PCILIB_DMA_TYPE_BLOCK, /**< Simple DMA engine */
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PCILIB_DMA_TYPE_PACKET, /**< Streaming (scatter-gather) DMA engine */
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PCILIB_DMA_TYPE_UNKNOWN
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} pcilib_dma_engine_type_t;
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pcilib_dma_engine_addr_t addr;
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pcilib_dma_engine_type_t type;
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pcilib_dma_direction_t direction;
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pcilib_dma_engine_addr_t addr; /**< Address of DMA engine (from 0) */
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pcilib_dma_engine_type_t type; /**< Type of DMA engine */
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pcilib_dma_direction_t direction; /**< Defines which kind of transfer does engine support: C2S, S2C, or both */
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size_t addr_bits; /**< Number of addressable bits in the system memory (we currently work with 32-bits only) */
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const char *description;
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const char *name; /**< Defines a short name of engine (its main use, i.e. main, auxilliary, etc.) */
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const char *description; /**< Defines a longer description of the engine */
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} pcilib_dma_engine_description_t;
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} pcilib_dma_buffer_status_t;
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const pcilib_dma_api_description_t *api;
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const pcilib_register_bank_description_t *banks;
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const pcilib_register_description_t *registers;
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const pcilib_dma_engine_description_t *engines;
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const char *description;
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const pcilib_dma_api_description_t *api; /**< Defines all API functions for DMA operation */
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const pcilib_register_bank_description_t *banks; /**< Pre-defined register banks exposed by DMA interface, additional banks can be defined during DMA initialization */
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const pcilib_register_description_t *registers; /**< Pre-defined registers exposed by DMA interface, additional registers can be defined during DMA initialization */
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const pcilib_dma_engine_description_t *engines; /**< List of DMA engines exposed by DMA interface, alternatively engines can be added during DMA initialization */
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const char *model; /**< If NULL, the actually used event model is used instead */
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const void *args; /**< Custom DMA-specific arguments. The actual structure may depend on the specified model */
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const char *name; /**< Short name of DMA interface */
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const char *description; /**< A bit longer description of DMA interface */
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} pcilib_dma_description_t;
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const pcilib_dma_description_t *pcilib_get_dma_info(pcilib_t *ctx);
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const pcilib_dma_description_t *pcilib_get_dma_description(pcilib_t *ctx);
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pcilib_dma_engine_t pcilib_add_dma_engine(pcilib_t *ctx, pcilib_dma_engine_description_t *desc);
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int pcilib_get_dma_status(pcilib_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers);
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int pcilib_init_dma(pcilib_t *ctx);