75
75
err = PCILIB_ERROR_INVALID_DATA; \
78
#define LOCK(lock_name) \
79
err = pcilib_try_lock(ctx->lock_name##_lock); \
81
pcilib_error("IPECamera is busy"); \
82
return PCILIB_ERROR_BUSY; \
84
ctx->lock_name##_locked = 1;
86
#define UNLOCK(lock_name) \
87
if (ctx->lock_name##_locked) { \
88
pcilib_unlock(ctx->lock_name##_lock); \
89
ctx->lock_name##_locked = 0; \
79
92
pcilib_context_t *ipecamera_init(pcilib_t *pcilib) {
89
102
memset(ctx, 0, sizeof(ipecamera_t));
104
ctx->run_lock = pcilib_get_lock(pcilib, PCILIB_LOCK_FLAGS_DEFAULT, "ipecamera");
105
ctx->stream_lock = pcilib_get_lock(pcilib, PCILIB_LOCK_FLAGS_DEFAULT, "ipecamera/stream");
106
ctx->trigger_lock = pcilib_get_lock(pcilib, PCILIB_LOCK_FLAGS_DEFAULT, "ipecamera/trigger");
108
if (!ctx->run_lock||!ctx->stream_lock||!ctx->trigger_lock) {
110
pcilib_error("Failed to initialize locks to protect ipecamera operation");
91
114
ctx->buffer_size = IPECAMERA_DEFAULT_BUFFER_SIZE;
93
116
ctx->dim.bpp = sizeof(ipecamera_pixel_t) * 8;
153
176
ipecamera_t *ctx = (ipecamera_t*)vctx;
154
177
ipecamera_stop(vctx, PCILIB_EVENT_FLAGS_DEFAULT);
179
if (ctx->trigger_lock)
180
pcilib_return_lock(vctx->pcilib, PCILIB_LOCK_FLAGS_DEFAULT, ctx->trigger_lock);
182
if (ctx->stream_lock)
183
pcilib_return_lock(vctx->pcilib, PCILIB_LOCK_FLAGS_DEFAULT, ctx->stream_lock);
186
pcilib_return_lock(vctx->pcilib, PCILIB_LOCK_FLAGS_DEFAULT, ctx->run_lock);
210
243
control = ctx->control_reg;
211
244
status = ctx->status_reg;
213
// Set Reset bit to CMOSIS
214
err = pcilib_write_register_by_id(pcilib, control, 0x1e4);
216
pcilib_error("Error setting FPGA reset bit");
219
usleep(IPECAMERA_CMOSIS_RESET_DELAY);
248
ipecamera_debug(API, "ipecamera: starting");
250
if (ctx->firmware == IPECAMERA_FIRMWARE_UFO5) {
251
// Set Reset bit to CMOSIS
252
err = pcilib_write_register_by_id(pcilib, control, 0x1e4);
255
pcilib_error("Error setting FPGA reset bit");
258
usleep(IPECAMERA_CMOSIS_RESET_DELAY);
221
260
// Remove Reset bit to CMOSIS
222
err = pcilib_write_register_by_id(pcilib, control, 0x1e1);
224
pcilib_error("Error reseting FPGA reset bit");
227
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
261
err = pcilib_write_register_by_id(pcilib, control, 0x1e1);
264
pcilib_error("Error reseting FPGA reset bit");
267
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
229
269
// Special settings for CMOSIS v.2
230
value = 01; err = pcilib_write_register_space(pcilib, "cmosis", 115, 1, &value);
232
pcilib_error("Error setting CMOSIS configuration");
235
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
270
value = 01; err = pcilib_write_register_space(pcilib, "cmosis", 115, 1, &value);
273
pcilib_error("Error setting CMOSIS configuration");
276
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
237
value = 07; err = pcilib_write_register_space(pcilib, "cmosis", 82, 1, &value);
239
pcilib_error("Error setting CMOSIS configuration");
278
value = 07; err = pcilib_write_register_space(pcilib, "cmosis", 82, 1, &value);
281
pcilib_error("Error setting CMOSIS configuration");
284
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
285
pcilib_warning("Reset procedure is not complete");
287
pcilib_warning("Reset procedure is not implemented");
242
usleep(IPECAMERA_CMOSIS_REGISTER_DELAY);
244
290
// Set default parameters
245
291
err = pcilib_write_register_by_id(pcilib, control, IPECAMERA_IDLE);
247
294
pcilib_error("Error bringing FPGA in default mode");
256
303
err = pcilib_read_register_by_id(pcilib, status, &value);
258
306
if (err) pcilib_error("Error reading status register");
259
307
else pcilib_error("Camera returns unexpected status (status: %lx)", value);
261
309
return PCILIB_ERROR_VERIFY;
264
return pcilib_skip_dma(vctx->pcilib, ctx->rdma);
312
err = pcilib_skip_dma(vctx->pcilib, ctx->rdma);
315
ipecamera_debug(API, "ipecamera: reset done");
645
705
GET_REG(status2_reg, value);
646
706
} while ((value&0x40000000)&&(pcilib_calc_time_to_deadline(&deadline) > 0));
648
if (value&0x40000000)
708
if (value&0x40000000) {
649
709
#endif /* IPECAMERA_TRIGGER_WAIT_IDLE */
650
711
return PCILIB_ERROR_BUSY;
712
#ifdef IPECAMERA_TRIGGER_TIMEOUT
714
#endif /* IPECAMERA_TRIGGER_WAIT_IDLE */
653
717
GET_REG(control_reg, value);