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* Few fixesSuren A. Chilingaryan2011-07-124-14/+34
* Separate NWL loopback code, provide DMA start/stop interfacesSuren A. Chilingaryan2011-07-1211-82/+181
* Another reorganization of NWL sourcesSuren A. Chilingaryan2011-07-127-286/+302
* Provide IRQ enable/disable callSuren A. Chilingaryan2011-07-1210-30/+171
* Suppport DMA modes in console application (not functional yet)Suren A. Chilingaryan2011-07-1212-33/+233
* Few fixesSuren A. Chilingaryan2011-07-122-8/+25
* Fix compilation issuesSuren A. Chilingaryan2011-07-113-8/+8
* Reorganization of NWL engine, step 1Suren A. Chilingaryan2011-07-115-128/+176
* Wait for the completion of DMA operations during writesSuren A. Chilingaryan2011-07-119-349/+431
* Minor improvementSuren A. Chilingaryan2011-07-111-7/+7
* Change cli parameters (reserve -t parameter for future use as timeout)Suren A. Chilingaryan2011-07-111-25/+41
* IRQ support in NWL DMA engineSuren A. Chilingaryan2011-07-1118-206/+306
* Support dynamic registers, support register offsets and multiregisters (bitma...Suren A. Chilingaryan2011-07-0916-202/+468
* Add some check to verify if NWL DMA engine have been successfully initializedSuren A. Chilingaryan2011-07-081-5/+3
* Support alignments in kmem allocationSuren A. Chilingaryan2011-07-063-12/+21
* Fix segmentation failure in DMA access modeSuren A. Chilingaryan2011-07-061-1/+5
* Compilation fixSuren A. Chilingaryan2011-07-061-4/+4
* A bit of renamingSuren A. Chilingaryan2011-07-069-55/+51
* Include type in the register descriptionSuren A. Chilingaryan2011-07-063-60/+62
* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-0611-571/+785
* Define addresses of NWL enginesroot2011-07-041-1/+3
* North West Logick DMA implementationroot2011-07-0422-227/+1367
* DMA engine initialization and basic intrastructure for DMA read/writeroot2011-06-185-27/+189
* Enumerate DMA enginesroot2011-06-179-25/+255
* New reset routineroot2011-06-161-3/+3
* A bit of DMA infrastructureroot2011-06-167-24/+126
* Remove unsupported devicesroot2011-06-164-83/+8
* Move to new FPGA designroot2011-06-168-82/+179
* 32 bit fixSuren A. Chilingaryan2011-06-071-1/+1
* Do not crash if model is not definedSuren A. Chilingaryan2011-05-181-6/+8
* Some improvements in error handlingSuren A. Chilingaryan2011-05-031-12/+40
* Multiline grabbingSuren A. Chilingaryan2011-05-031-135/+180
* A bit faster datacpySuren A. Chilingaryan2011-05-021-10/+17
* Alternative way to overcome problem with address verification of CMOSIS regis...Suren A. Chilingaryan2011-04-141-24/+26
* Rearrange channels to get proper imageSuren A. Chilingaryan2011-04-141-4/+20
* Introduce pcilib_context_t type instead pointer to voidSuren A. Chilingaryan2011-04-145-34/+35
* Accept timeout parameter to get_next_event callSuren A. Chilingaryan2011-04-144-7/+12
* Support non-callback way of getting eventsSuren A. Chilingaryan2011-04-145-2/+65
* Fix order of pixels, temporaly disable some checks to work with current FPGA ...Suren A. Chilingaryan2011-04-141-9/+44
* Set correct hexdecimal values of registers during IPECamera reset and readout...Suren A. Chilingaryan2011-04-131-13/+19
* Support simplified mode (slow) of writting CMOSIS sensors: issue 3 writes + d...Suren A. Chilingaryan2011-04-131-23/+84
* Support quiete mode to suppress warningsSuren A. Chilingaryan2011-04-131-2/+14
* Add special CMOSIS registersSuren A. Chilingaryan2011-04-131-0/+2
* Really fix setting registers with access mode equal to 32 (size of pcilib_reg...Suren A. Chilingaryan2011-04-131-2/+2
* clean upSuren A. Chilingaryan2011-04-123-2/+3
* Small bug fix: forgot to set a flag indicating what we are startedSuren A. Chilingaryan2011-04-121-2/+6
* Start a ToDo listSuren A. Chilingaryan2011-04-121-0/+2
* Look for headers in the current directorySuren A. Chilingaryan2011-04-121-1/+1
* Comment out the failing registerSuren A. Chilingaryan2011-04-121-1/+1
* Allow access to implementation context and provide call to set size of intern...Suren A. Chilingaryan2011-04-126-2/+38
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