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authorSuren A. Chilingaryan <csa@dside.dyndns.org>2011-04-13 20:01:27 +0200
committerSuren A. Chilingaryan <csa@dside.dyndns.org>2011-04-13 20:01:27 +0200
commitb5eac3af41cb8c752b6779dd36c314f8f6caeccf (patch)
tree339d0579670851e3ba22a5a0bb642b2b9f75724f
parentf44f8881c89fcb2e6e59a64dd1401cc8097d1306 (diff)
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Really fix setting registers with access mode equal to 32 (size of pcilib_register_value_t)
-rw-r--r--pci.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/pci.c b/pci.c
index 5fae55c..a3f09db 100644
--- a/pci.c
+++ b/pci.c
@@ -604,8 +604,8 @@ int pcilib_write_register_by_id(pcilib_t *ctx, pcilib_register_t reg, pcilib_reg
pcilib_error("Big-endian byte order support is not implemented");
return PCILIB_ERROR_NOTSUPPORTED;
} else {
- if (b->access == sizeof(res) * 8) {
- buf[i] = res;
+ if (b->access == sizeof(pcilib_register_value_t) * 8) {
+ buf[0] = value;
} else {
for (i = 0, res = value; (res > 0)&&(i <= n); ++i) {
buf[i] = res & BIT_MASK(b->access);