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authorSuren A. Chilingaryan <csa@suren.me>2015-08-12 20:57:37 +0200
committerSuren A. Chilingaryan <csa@suren.me>2015-08-12 20:57:37 +0200
commit5001621745651443d3825a30a92897cac7f1ec53 (patch)
tree15522e3620947547a0c57a3b9a97c2729ac6fefb /pcilib
parent55783eb24e983786056f4ba7925aa23fca13c79e (diff)
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Do not fail if PCI configuration is not fully available to unprivileged user
Diffstat (limited to 'pcilib')
-rw-r--r--pcilib/pci.c11
-rw-r--r--pcilib/pci.h1
2 files changed, 9 insertions, 3 deletions
diff --git a/pcilib/pci.c b/pcilib/pci.c
index 4351c1e..62ac92d 100644
--- a/pcilib/pci.c
+++ b/pcilib/pci.c
@@ -425,11 +425,16 @@ static int pcilib_update_pci_configuration_space(pcilib_t *ctx) {
}
size = read(ctx->pci_cfg_space_fd, ctx->pci_cfg_space_cache, 256);
- if (size != 256) {
- pcilib_error("Failed to read PCI configuration from sysfs");
+ if (size < 64) {
+ if (size <= 0)
+ pcilib_error("Failed to read PCI configuration from sysfs, errno: %i", errno);
+ else
+ pcilib_error("Failed to read PCI configuration from sysfs, only %zu bytes read (expected at least 64)", size);
return PCILIB_ERROR_FAILED;
}
+ ctx->pci_cfg_space_size = size;
+
return 0;
}
@@ -452,7 +457,7 @@ static uint32_t *pcilib_get_pci_capabilities(pcilib_t *ctx, int cap_id) {
cap = ctx->pci_cfg_space_cache[(0x34>>2)];
cap_offset = cap&0xFC;
- while ((cap_offset)&&(cap_offset < 256)) {
+ while ((cap_offset)&&(cap_offset < ctx->pci_cfg_space_size)) {
cap = ctx->pci_cfg_space_cache[cap_offset>>2];
if ((cap&0xFF) == cap_id)
return &ctx->pci_cfg_space_cache[cap_offset>>2];
diff --git a/pcilib/pci.h b/pcilib/pci.h
index 51bb352..340abd3 100644
--- a/pcilib/pci.h
+++ b/pcilib/pci.h
@@ -42,6 +42,7 @@ struct pcilib_s {
int pci_cfg_space_fd; /**< File descriptor linking to PCI configuration space in sysfs */
uint32_t pci_cfg_space_cache[64]; /**< Cached PCI configuration space */
+ size_t pci_cfg_space_size; /**< Size of the cached PCI configuration space, sometimes not fully is available for unpriveledged user */
const uint32_t *pcie_capabilities; /**< PCI Capbility structure (just a pointer at appropriate place in the pci_cfg_space) */
int reg_bar_mapped; /**< Indicates that all BARs used to access registers are mapped */