bzr branch
http://suren.me/webbzr/alps/pcitool
7.1.5
by Suren A. Chilingaryan
Support for FPGA registers |
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#include <sys/time.h> |
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#include <arpa/inet.h> |
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#include <assert.h> |
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#include "tools.h" |
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#include "model.h" |
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Support for FPGA registers |
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#include "error.h" |
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Documentation update |
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#include "bar.h" |
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#include "datacpy.h" |
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#include "pci.h" |
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by Suren A. Chilingaryan
Support for FPGA registers |
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#define default_datacpy(dst, src, access, bank) pcilib_datacpy(dst, src, access, 1, bank->raw_endianess)
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uintptr_t pcilib_default_resolve(pcilib_t *ctx, pcilib_register_bank_context_t *bank_ctx, pcilib_address_resolution_flags_t flags, pcilib_register_addr_t reg_addr) { |
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uintptr_t addr; |
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const pcilib_register_bank_description_t *b = bank_ctx->bank; |
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if (reg_addr == PCILIB_REGISTER_ADDRESS_INVALID) reg_addr = 0; |
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switch (flags&PCILIB_ADDRESS_RESOLUTION_MASK_ACCESS_MODE) { |
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case 0: |
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if (b->read_addr != b->write_addr) |
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return PCILIB_ADDRESS_INVALID; |
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case PCILIB_ADDRESS_RESOLUTION_FLAG_READ_ONLY: |
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addr = b->read_addr + reg_addr; |
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break; |
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case PCILIB_ADDRESS_RESOLUTION_FLAG_WRITE_ONLY: |
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addr = b->write_addr + reg_addr; |
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default: |
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return PCILIB_ADDRESS_INVALID; |
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}
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switch (flags&PCILIB_ADDRESS_RESOLUTION_MASK_ADDRESS_TYPE) { |
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case 0: |
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return (uintptr_t)pcilib_resolve_bar_address(ctx, b->bar, addr); |
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case PCILIB_ADDRESS_RESOLUTION_FLAG_BUS_ADDRESS: |
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case PCILIB_ADDRESS_RESOLUTION_FLAG_PHYS_ADDRESS: |
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return ctx->board_info.bar_start[b->bar] + addr; |
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}
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return PCILIB_ADDRESS_INVALID; |
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}
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int pcilib_default_read(pcilib_t *ctx, pcilib_register_bank_context_t *bank_ctx, pcilib_register_addr_t addr, pcilib_register_value_t *value) { |
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char *ptr; |
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pcilib_register_value_t val = 0; |
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const pcilib_register_bank_description_t *b = bank_ctx->bank; |
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int access = b->access / 8; |
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ptr = pcilib_resolve_bar_address(ctx, b->bar, b->read_addr + addr); |
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default_datacpy(&val, ptr, access, b); |
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Support dynamic registers, support register offsets and multiregisters (bitmasks), list NWL DMA registers |
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// *value = val&BIT_MASK(bits);
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*value = val; |
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return 0; |
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}
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int pcilib_default_write(pcilib_t *ctx, pcilib_register_bank_context_t *bank_ctx, pcilib_register_addr_t addr, pcilib_register_value_t value) { |
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char *ptr; |
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const pcilib_register_bank_description_t *b = bank_ctx->bank; |
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int access = b->access / 8; |
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ptr = pcilib_resolve_bar_address(ctx, b->bar, b->write_addr + addr); |
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default_datacpy(ptr, &value, access, b); |
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by Suren A. Chilingaryan
Support for FPGA registers |
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return 0; |
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}
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