From c95df4d43738e1597c348bc7f98ff2902574d720 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 16 Jun 2011 01:26:14 +0200 Subject: Move to new FPGA design --- default.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'default.c') diff --git a/default.c b/default.c index e01a623..f771599 100644 --- a/default.c +++ b/default.c @@ -17,8 +17,9 @@ int pcilib_default_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_value_t val = 0; int access = bank->access / 8; - ptr = pcilib_resolve_register_address(ctx, bank->read_addr + addr * access); + ptr = pcilib_resolve_register_address(ctx, bank->bar, bank->read_addr + addr * access); default_datacpy(&val, ptr, access, bank); +// printf("%lx %lx\n",val, BIT_MASK(bits)); *value = val&BIT_MASK(bits); @@ -32,7 +33,7 @@ int pcilib_default_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank char *ptr; int access = bank->access / 8; - ptr = pcilib_resolve_register_address(ctx, bank->write_addr + addr * access); + ptr = pcilib_resolve_register_address(ctx, bank->bar, bank->write_addr + addr * access); default_datacpy(ptr, &value, access, bank); return 0; -- cgit v1.2.3