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* Big redign of model structuresSuren A. Chilingaryan2015-04-201-7/+5
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* multithread preprocessing of ipecamera frames and code reorganizationSuren A. Chilingaryan2011-12-121-0/+1
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* Gathering a bit of statisticsSuren A. Chilingaryan2011-12-091-0/+1
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* Initial support of event streaming in cliSuren A. Chilingaryan2011-12-091-3/+6
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* new event architecture, first trialSuren A. Chilingaryan2011-12-081-0/+5
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* Implement DMA access synchronization for NWL implementationSuren A. Chilingaryan2011-07-171-2/+1
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* Implement DMA access synchronization in the driverSuren A. Chilingaryan2011-07-161-0/+7
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* Suppport DMA modes in console application (not functional yet)Suren A. Chilingaryan2011-07-121-0/+2
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* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-061-0/+2
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* North West Logick DMA implementationroot2011-07-041-0/+2
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* clean upSuren A. Chilingaryan2011-04-121-1/+1
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* Support for FPGA registersSuren A. Chilingaryan2011-03-091-0/+3
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* Initial support of IPECamera protocolSuren A. Chilingaryan2011-03-081-4/+16
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* Initial support for registers, infrastructure onlySuren A. Chilingaryan2011-02-181-1/+4
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* Print a bit more detailsSuren A. Chilingaryan2011-02-131-0/+1
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* Initial importSuren A. Chilingaryan2011-02-131-0/+5