| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2011-07-11 | Reorganization of NWL engine, step 1 | Suren A. Chilingaryan | |
| 2011-07-11 | Wait for the completion of DMA operations during writes | Suren A. Chilingaryan | |
| 2011-07-11 | IRQ support in NWL DMA engine | Suren A. Chilingaryan | |
| 2011-07-09 | Support dynamic registers, support register offsets and multiregisters ↵ | Suren A. Chilingaryan | |
| (bitmasks), list NWL DMA registers | |||
| 2011-07-08 | Add some check to verify if NWL DMA engine have been successfully initialized | Suren A. Chilingaryan | |
| 2011-07-06 | Support alignments in kmem allocation | Suren A. Chilingaryan | |
| 2011-07-06 | A bit of renaming | Suren A. Chilingaryan | |
| 2011-07-04 | Define addresses of NWL engines | root | |
| 2011-07-04 | North West Logick DMA implementation | root | |
| 2011-06-18 | DMA engine initialization and basic intrastructure for DMA read/write | root | |
| 2011-06-17 | Enumerate DMA engines | root | |
